CPU

The ARM® Cortex®-M4 processor with floating-point unit (FPU) has a 32-bit instruction set (Thumb®-2 technology) that implements a superset of 16 and 32-bit instructions to maximize code density and performance.

This processor implements several features that enable energy-efficient arithmetic and high-performance signal processing including:

The ARM Cortex Microcontroller Software Interface Standard (CMSIS) hardware abstraction layer for the ARM Cortex processor series is implemented and available for the M4 CPU.

Real-time execution is highly deterministic in thread mode, to and from sleep modes, and when handling events at configurable priority levels via the Nested Vectored Interrupt Controller (NVIC).

Executing code from flash will have a wait state penalty on the nRF52 Series. An instruction cache can be enabled to minimize flash wait states when fetching instructions. For more information on cache, see Cache. The section Electrical specification shows CPU performance parameters including wait states in different modes, CPU current and efficiency, and processing power and efficiency based on the CoreMark® benchmark.

Floating point interrupt

The floating point unit (FPU) may generate exceptions when used due to e.g. overflow or underflow. These exceptions will trigger the FPU interrupt (see Instantiation). To clear the IRQ line when an exception has occurred, the relevant exception bit within the FPSCR register needs to be cleared. For more information about the FPSCR or other FPU registers, see Cortex-M4 Devices Generic User Guide.

Electrical specification

CPU performance

The CPU clock speed is 64 MHz. Current and efficiency data is taken when in System ON and the CPU is executing the CoreMark™ benchmark. It includes power regulator and clock base currents. All other blocks are IDLE.

Symbol Description Min. Typ. Max. Units
WFLASH

CPU wait states, running from flash, cache disabled

0 2  
WFLASHCACHE

CPU wait states, running from flash, cache enabled

0 3  
WRAM

CPU wait states, running from RAM

0  
IDDFLASHCACHE

CPU current, running from flash, cache enabled, LDO

7.4 mA
IDDFLASHCACHEDCDC

CPU current, running from flash, cache enabled, DCDC 3V

3.7 mA
IDDFLASH

CPU current, running from flash, cache disabled, LDO

8.0 mA
IDDFLASHDCDC

CPU current, running from flash, cache disabled, DCDC 3V

3.9 mA
IDDRAM

CPU current, running from RAM, LDO

6.7 mA
IDDRAMDCDC

CPU current, running from RAM, DCDC 3V

3.3 mA
IDDFLASH/MHz

CPU efficiency, running from flash, cache enabled, LDO

125 µA/MHz
IDDFLASHDCDC/MHz

CPU efficiency, running from flash, cache enabled, DCDC 3V

58 µA/MHz
CMFLASH

CoreMark1, running from flash, cache enabled

215 CoreMark
CMFLASH/MHz

CoreMark per MHz, running from flash, cache enabled

3.36 CoreMark/MHz
CMFLASH/mA

CoreMark per mA, running from flash, cache enabled, DCDC 3V

58 CoreMark/mA

CPU and support module configuration

The ARM® Cortex®-M4 processor has a number of CPU options and support modules implemented on the device.

Option / Module Description Implemented
Core options
NVIC Nested Vector Interrupt Controller 37 vectors
PRIORITIES Priority bits 3
WIC Wakeup Interrupt Controller NO
Endianness Memory system endianness Little endian
Bit Banding Bit banded memory NO
DWT Data Watchpoint and Trace YES
SysTick System tick timer YES
Modules
MPU Memory protection unit YES
FPU Floating point unit YES
DAP Debug Access Port YES
ETM Embedded Trace Macrocell YES
ITM Instrumentation Trace Macrocell YES
TPIU Trace Port Interface Unit YES
ETB Embedded Trace Buffer NO
FPB Flash Patch and Breakpoint Unit YES
HTM AHB Trace Macrocell NO
1 Using IAR v6.50.1.4452 with flags --endian=little --cpu=Cortex-M4 -e --fpu=VFPv4_sp –Ohs --no_size_constraints

Documentation feedback | Developer Zone | Updated 2017-10-11