LPCOMP — Low power comparator

LPCOMP compares an input voltage against a reference voltage.

Listed here are the main features of LPCOMP:

In System ON, the LPCOMP can generate separate events on rising and falling edges of a signal, or sample the current state of the pin as being above or below the selected reference. The block can be configured to use any of the analog inputs on the device. Additionally, the low power comparator can be used as an analog wakeup source from System OFF or System ON. The comparator threshold can be programmed to a range of fractions of the supply voltage.

Restriction: LPCOMP cannot be used (STARTed) at the same time as COMP. Only one comparator can be used at a time.
Figure 1. Low power comparator

The wakeup comparator (LPCOMP) compares an input voltage (VIN+), which comes from an analog input pin selected via the PSEL register against a reference voltage (VIN-) selected via the REFSEL and EXTREFSEL registers.

The PSEL, REFSEL, and EXTREFSEL registers must be configured before the LPCOMP is enabled through the ENABLE register.

The HYST register allows enabling an optional hysteresis in the comparator core. This hysteresis is in the order of magnitude of 50 mV, and shall prevent noise on the signal to create unwanted events. See Figure 2 for illustration of the effect of an active hysteresis on a noisy input signal. It is disabled by default, and shall be configured before enabling LPCOMP as well.

The LPCOMP is started by triggering the START task. After a start-up time of tLPCOMP,STARTUP the LPCOMP will generate a READY event to indicate that the comparator is ready to use and the output of the LPCOMP is correct. The LPCOMP will generate events every time VIN+ crosses VIN-. More specifically, every time VIN+ rises above VIN- (upward crossing) an UP event is generated along with a CROSS event. Every time VIN+ falls below VIN- (downward crossing), a DOWN event is generated along with a CROSS event. When hysteresis is enabled, the upward crossing level becomes (VIN- + VHYST/2), and the downward crossing level becomes (VIN- - VHYST/2).

The LPCOMP is stopped by triggering the STOP task.

Figure 2. Effect of hysteresis on a noisy input signal

LPCOMP will be operational in both System ON and System OFF mode when it is enabled through the ENABLE register. See POWER — Power supply for more information about power modes. Note that it is not allowed to go to System OFF when a READY event is pending to be generated.

All LPCOMP registers, including ENABLE, are classified as retained registers when the LPCOMP is enabled. However, when the device wakes up from System OFF, all LPCOMP registers will be reset.

The LPCOMP can wake up the system from System OFF by asserting the ANADETECT signal. The ANADETECT signal can be derived from any of the event sources that generate the UP, DOWN and CROSS events. In case of wakeup from System OFF, no events will be generated, only the ANADETECT signal. See the ANADETECT register (ANADETECT) for more information on how to configure the ANADETECT signal.

The immediate value of the LPCOMP can be sampled to RESULT by triggering the SAMPLE task.

See RESETREAS for more information on how to detect a wakeup from LPCOMP.

Shared resources

The LPCOMP shares resources with other peripherals.

The LPCOMP shares analog resources with SAADC and COMP. While it is possible to use SAADC at the same time as COMP or LPCOMP, COMP and LPCOMP are mutually exclusive: enabling one will automatically disable the other. In addition, when using SAADC and COMP or LPCOMP simultaneously, it is not possible to select the same analog input pin for both modules.

The LPCOMP peripheral shall not be disabled (by writing to the ENABLE register) before the peripheral has been stopped. Failing to do so may result in unpredictable behaviour.

Pin configuration

You can use the LPCOMP.PSEL register to select one of the analog input pins, AIN0 through AIN7, as the analog input pin for the LPCOMP.

See GPIO — General purpose input/output for more information about the pins. Similarly, you can use EXTREFSEL to select one of the analog reference input pins, AIN0 and AIN1, as input for AREF in case AREF is selected in EXTREFSEL. The selected analog pins will be acquired by the LPCOMP when it is enabled through ENABLE.

Registers

Table 1. Instances
Base address Peripheral Instance Description Configuration
0x40013000 LPCOMP LPCOMP

Low power comparator

   
Table 2. Register Overview
Register Offset Description
TASKS_START 0x000

Start comparator

 
TASKS_STOP 0x004

Stop comparator

 
TASKS_SAMPLE 0x008

Sample comparator value

 
EVENTS_READY 0x100

LPCOMP is ready and output is valid

 
EVENTS_DOWN 0x104

Downward crossing

 
EVENTS_UP 0x108

Upward crossing

 
EVENTS_CROSS 0x10C

Downward or upward crossing

 
SHORTS 0x200

Shortcut register

 
INTENSET 0x304

Enable interrupt

 
INTENCLR 0x308

Disable interrupt

 
RESULT 0x400

Compare result

 
ENABLE 0x500

Enable LPCOMP

 
PSEL 0x504

Input pin select

 
REFSEL 0x508

Reference select

 
EXTREFSEL 0x50C

External reference select

 
ANADETECT 0x520

Analog detect configuration

 
HYST 0x538

Comparator hysteresis enable

 

SHORTS

Address offset: 0x200

Shortcut register

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                       E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

READY_SAMPLE

   

Shortcut between READY event and SAMPLE task

See EVENTS_READY and TASKS_SAMPLE

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

B RW

READY_STOP

   

Shortcut between READY event and STOP task

See EVENTS_READY and TASKS_STOP

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

C RW

DOWN_STOP

   

Shortcut between DOWN event and STOP task

See EVENTS_DOWN and TASKS_STOP

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

D RW

UP_STOP

   

Shortcut between UP event and STOP task

See EVENTS_UP and TASKS_STOP

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

E RW

CROSS_STOP

   

Shortcut between CROSS event and STOP task

See EVENTS_CROSS and TASKS_STOP

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

 

INTENSET

Address offset: 0x304

Enable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                         D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

READY

   

Write '1' to Enable interrupt for READY event

See EVENTS_READY

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

B RW

DOWN

   

Write '1' to Enable interrupt for DOWN event

See EVENTS_DOWN

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

C RW

UP

   

Write '1' to Enable interrupt for UP event

See EVENTS_UP

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

D RW

CROSS

   

Write '1' to Enable interrupt for CROSS event

See EVENTS_CROSS

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

 

INTENCLR

Address offset: 0x308

Disable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                         D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

READY

   

Write '1' to Disable interrupt for READY event

See EVENTS_READY

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

B RW

DOWN

   

Write '1' to Disable interrupt for DOWN event

See EVENTS_DOWN

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

C RW

UP

   

Write '1' to Disable interrupt for UP event

See EVENTS_UP

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

D RW

CROSS

   

Write '1' to Disable interrupt for CROSS event

See EVENTS_CROSS

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

 

RESULT

Address offset: 0x400

Compare result

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A R

RESULT

   

Result of last compare. Decision point SAMPLE task.

     

Bellow

0

Input voltage is below the reference threshold (VIN+ < VIN-).

Deprecated

     

Below

0

Input voltage is below the reference threshold (VIN+ < VIN-).

     

Above

1

Input voltage is above the reference threshold (VIN+ > VIN-).

 

ENABLE

Address offset: 0x500

Enable LPCOMP

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                             A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

ENABLE

   

Enable or disable LPCOMP

     

Disabled

0

Disable

     

Enabled

1

Enable

 

PSEL

Address offset: 0x504

Input pin select

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                           A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

PSEL

   

Analog pin select

     

AnalogInput0

0

AIN0 selected as analog input

     

AnalogInput1

1

AIN1 selected as analog input

     

AnalogInput2

2

AIN2 selected as analog input

     

AnalogInput3

3

AIN3 selected as analog input

     

AnalogInput4

4

AIN4 selected as analog input

     

AnalogInput5

5

AIN5 selected as analog input

     

AnalogInput6

6

AIN6 selected as analog input

     

AnalogInput7

7

AIN7 selected as analog input

 

REFSEL

Address offset: 0x508

Reference select

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                         A A A A
Reset 0x00000004 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
Id RW Field Value Id Value Description
A RW

REFSEL

   

Reference select

     

Ref1_8Vdd

0

VDD * 1/8 selected as reference

     

Ref2_8Vdd

1

VDD * 2/8 selected as reference

     

Ref3_8Vdd

2

VDD * 3/8 selected as reference

     

Ref4_8Vdd

3

VDD * 4/8 selected as reference

     

Ref5_8Vdd

4

VDD * 5/8 selected as reference

     

Ref6_8Vdd

5

VDD * 6/8 selected as reference

     

Ref7_8Vdd

6

VDD * 7/8 selected as reference

     

ARef

7

External analog reference selected

     

Ref1_16Vdd

8

VDD * 1/16 selected as reference

     

Ref3_16Vdd

9

VDD * 3/16 selected as reference

     

Ref5_16Vdd

10

VDD * 5/16 selected as reference

     

Ref7_16Vdd

11

VDD * 7/16 selected as reference

     

Ref9_16Vdd

12

VDD * 9/16 selected as reference

     

Ref11_16Vdd

13

VDD * 11/16 selected as reference

     

Ref13_16Vdd

14

VDD * 13/16 selected as reference

     

Ref15_16Vdd

15

VDD * 15/16 selected as reference

 

EXTREFSEL

Address offset: 0x50C

External reference select

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                           A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

EXTREFSEL

   

External analog reference select

     

AnalogReference0

0

Use AIN0 as external analog reference

     

AnalogReference1

1

Use AIN1 as external analog reference

 

ANADETECT

Address offset: 0x520

Analog detect configuration

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                             A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

ANADETECT

   

Analog detect configuration

     

Cross

0

Generate ANADETECT on crossing, both upward crossing and downward crossing

     

Up

1

Generate ANADETECT on upward crossing only

     

Down

2

Generate ANADETECT on downward crossing only

 

HYST

Address offset: 0x538

Comparator hysteresis enable

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

HYST

   

Comparator hysteresis enable

     

NoHyst

0

Comparator hysteresis disabled

     

Hyst50mV

1

Comparator hysteresis disabled (typ. 50 mV)

 

Electrical specification

LPCOMP Electrical Specification

Symbol Description Min. Typ. Max. Units
ILPC

Run current for low power comparator

0.5 µA
tLPCANADET

Time from VIN crossing (>=50mV above threshold) to ANADETECT signal generated.

5 µs
EREFLADDER

Error in reference ladder threshold voltage

-30 30 mV
VHYST

Optional hysteresis

30 mV

Documentation feedback | Developer Zone | Updated 2017-10-11