nRF5 SDK v17.1.0
SPI RAW protocol
This information applies to the following SoftDevices: S132, S140

The SPI RAW protocol implements the Serialization PHY API for the SPI interface.

In the standard implementation, the SPI RAW interface uses six lines: four standard ones (CLK, MOSI, MISO, /CS) and two additional ones (/RDY, /REQ). The application chip is an SPI bus master, while the connectivitz chip is a slave device. A 5-wire variant, which does not use the /RDY line (SPI_5W RAW protocol), is also implemented.

The SPI RAW protocol facilitates the transfer of packets with variable length. Due to variable length of the packets and the master-slave architecture of the SPI interface, each packet transfer is done in simplex mode. Every bus transaction transfers data either from the application chip to the connectivity chip or from the connectivity chip to the application chip, but not simultaneously in both directions. Transfer of data consists of bus transactions. Each transaction starts with falling edge and ends with rising edge of the /CS signal. Read transactions are not interleaved with write transactions. Once started, all transactions needed to read or write the whole packet must be completed.

Both the /REQ and /RDY lines are active low and driven by the slave device. Line /REQ, when asserted, signals that the slave device has data to be read. Line /RDY, when asserted, signals that the slave device is ready for a transaction.

Payload transfer is preceded by two bytes of physical layer header, which defines the size of the packet. The header is transmitted as least significant byte first. The SPI slave device uses DMA, and due to the maximum size of DMA buffers, packets are divided into frames. The size of a frame is determined by the MTU constant, which is currently set to 255 (SER_PHY_SPI_MTU_SIZE = 255). All packets bigger than MTU are divided into frames with maximum size of MTU. For example, a packet of the length of 1024 bytes will be divided into five frames (1024= 4x255 + 4):

[255][255][255][255][4]

Each frame is transferred as one bus transaction. MTU size may be set to a lower value to accommodate a different architecture of the master device.

SPI RAW - packet writing

Packets are transmitted in the following format:

TX_RAW_PACKET = [TX_HEADER][TX_FRAME][TX_FRAME][TX_FRAME]...
spi_6W_tx.png
Transmission of a single packet
  1. Packet length is sent as a [TX_HEADER]=[0x0004] in the first transaction.
  2. When the transaction ends, signal /RDY is deasserted by the slave device.
  3. After about 100 us, when DMA buffers are serviced and set for next transaction, the /RDY line is asserted again.
  4. The second transaction transfers payload [TX_FRAME]=[0x00, 0x78, 0x00, 0x03].

SPI RAW - packet reading

Packets are received in the following format:

SPI_RAW_PACKET = [ZERO_HEADER][RX_HEADER][RX_FRAME][RX_FRAME][RX_FRAME]...
spi_6W_rx.png
Reception of a packet
  1. Slave request for reading of a packet is signaled by assertion of the /REQ line.
  2. When the master device is ready to read a packet, it sends [ZERO_HEADER]=[0x0000]. The [ZERO_HEADER] is an indication that the master device is initiating a packet read operation.
  3. When [ZERO_HEADER] is detected by the slave, the /REQ line is deasserted.
  4. In the next transaction, a [RX_HEADER]=[0x0006], which defines the received payload length, is read by the master device.
  5. The third transaction transfers the payload of six bytes [RX_FRAME]=[0x01, 0x7C, 0x00, 0x00, 0x00, 0x00].

Master device driver

The SPI RAW protocol for the master device is implemented in the ser_phy_spi_phy_driver_master file. The operation of the ser_phy_switch_state() function is illustrated by the following UML state diagram:

app_uml1.svg
UML state diagram for the master device

Slave device driver

The SPI RAW protocol for the slave device is implemented in the ser_phy_spi_phy_driver_slave file. The operation of the spi_slave_event_handle() function is illustrated by the following UML state diagram:

conn_uml1.svg
UML state diagram for the slave device

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