nRF5 SDK v17.1.0
SPI_5W RAW protocol
This information applies to the following SoftDevices: S132, S140

The SPI_5W RAW protocol implements the Serialization PHY API for the SPI interface.

In the 5W implementation, the SPI interface uses five lines: four standard ones (CLK, MOSI, MISO, /CS) and one additional one - /REQ. The application chip is an SPI bus master, while the connectivity chip acts as a slave device.

In principle, the operation of SPI_5W is similar to the standard six-wire implementation (SPI RAW protocol). The major difference is lack of the /RDY line, which in the six-wire implementation is used to indicate readiness of the slave device for a data transaction. Without the /RDY line, the master device has to speculate by initiating transfer without prior knowledge if the slave device is ready to accept data. To distinguish transactions with a slave device that is ready for data from transactions with a slave device that is not ready for data, signaling on the MISO line is used.

The nRF5 SPI slave device hardware clocks out a DEFAULT byte (programmed as [0xFF]) when the device is not ready for data transaction. Because only the MISO line is used for signaling of the READY state, it works differently during write and read operations.

For packet writing, signaling is straightforward. When the slave device is ready for data, it clocks out a zero [0x00] for all data bytes. The same rule applies when a packet is read, but only for the first byte in each transaction. The physical layer driver precedes each reading transaction with a 'guard byte' [0x00].

If during a read or write operation, the master detects an invalid (non-zero) guard byte, the transaction is aborted (/CS is deasserted) and the master device initiates a new transaction. Backoff is determined by the time required for processing the interrupts and for resetting the internal state machines.

The size of MTU defines the size of physical frames. Due to the guard byte overhead, the effective frame size is smaller by one byte in read transactions. The SPI_5W driver is controlled by the __SPI_5W__ flag. If the __SPI_5W__ flag is not defined, line /RDY is used as in a standard six-wire implementation, but with frames including the guard byte.

SPI_5W RAW - packet writing

Packets are transmitted in the following format:

TX_RAW_PACKET = [TX_HEADER][TX_FRAME][TX_FRAME][TX_FRAME]...
spi_5W_tx.png
Transmission of a single packet
  1. Packet length is sent as [TX_HEADER]=[0x0004] in the first transaction. Because the first byte of data clocked in [0x0000] is a valid guard byte, the transaction is considered to be successful.
  2. The second transaction attempts to transfer the payload [TX_FRAME]=[0x00, 0x78, 0x41, 0x03], but due to invalid guard byte, it is aborted.
  3. During the third transaction, a valid guard byte is clocked in and the transaction is completed. Note that the /RDY line is deasserted during transaction because it is not driven by the slave device.

SPI_5W RAW packet reading

Packets are received in the following format:

SPI_RAW_PACKET = [ZERO_HEADER][RX_HEADER][RX_FRAME][RX_FRAME][RX_FRAME]...
spi_5W_rx.png
Reception of a packet
  1. Slave request for reading of a packet is signaled by assertion of the /REQ line.
  2. When the master device is ready to read a packet, it sends a [ZERO_HEADER] =[0x0000]. The [ZERO_HEADER] is used as indication that the master device initiates a packet read operation.
  3. When [ZERO_HEADER] is detected by the slave, the /REQ line is deasserted.
  4. In the next transaction, [RX_HEADER] =[0x00][0x0006] is read. The first byte in [RX_HEADER] is a valid guard byte which indicates that the remainder of the payload has meaningful data.
  5. In the third transaction, the guard byte, together with a payload of six bytes [0x00][0x01, 0x78, 0x00, 0x00, 0x00, 0x00], is clocked in.

Master device driver

The SPI_5W RAW protocol for the master device is implemented in the ser_phy_spi_5W_master file. The operation of ser_phy_switch_state() is almost identical as for the standard driver Master device driver, except for the fact that the slave device is assumed to be always READY. Therefore, when interpreting the graph, assume that the RDY flag is always TRUE and that there is no RDY_EVT event. Once the transaction is scheduled by the PHY driver, its execution is controlled by the adaptation state machine, which captures events from the hardware driver. Operation of the adaptation state machine is illustrated by the following UML state diagram:

adapt_5W_uml1.svg
UML state machine for the adaptation layer

If the __SPI_5W__ flag is not defined, the adaptation layer is disabled and line /RDY is used as in the standard six-wire implementation.

Slave device driver

The SPI RAW protocol for the slave device is implemented in the ser_phy_spi_5W_slave file. The operation spi_slave_event_handle() is almost identical as in the standard driver Slave device driver, except for the fact that line /RDY is not driven. If the __SPI_5W__ flag is not defined, line /RDY is used as in the standard six-wire implementation.


Documentation feedback | Developer Zone | Subscribe | Updated