The nRF9161 supports ETM and ITM trace.

Available trace sinks:

Trace data from the ETM and the ITM can be sent to an internal embedded trace buffer (ETB) or an external debugger via a 4-bit wide parallel trace port (TPIU), see TRACEDATA[0] through TRACEDATA[3], and TRACECLK in Debug and trace overview.

The following diagram shows the trace components architecture of the device's embedded Arm® CoreSight™ subsystem.

Figure 1. Trace components architecture
Trace components architecture

The standard Arm® components are documented in Arm CoreSight SoC-400 Technical Reference Manual, revision r3p2. For details on how to use the trace capabilities, please read the debug documentation of your IDE.

TPIU's trace pins are multiplexed with GPIOs, see Pin assignments for more information.

Note: To configure the trace data delivery to the device trace port, use the MDK system start-up file included as of MDK version 8.26.0.

Trace speed is configured in the TRACEPORTSPEED (Retained) register. The speed of the trace pins depends on the DRIVE setting of the GPIOs that the trace pins are multiplexed with. See GPIO — General purpose input/output for information about how to set drive settings. Only S0S1 and H0H1 drives are suitable for debugging. S0S1 is the default DRIVE at reset. If parallel or serial trace port signals are not fast enough in the debugging conditions, all GPIOs in use for tracing should be set to high drive (H0H1). The user shall make sure that DRIVE setting for these GPIOs is not overwritten by software during the debugging session.