Clock management

The clock control system can source the system clocks from a range of high and low frequency oscillators, and distribute them to modules based upon a module's individual requirements. Clock generation and distribution is handled automatically by PMU to optimize current consumption.

Listed here are the available clock signal sources:

The clock and oscillator resources are configured and controlled via the CLOCK peripheral as illustrated below.

Figure 1. Clock and oscillator setup
Clock and oscillator setup

HFCLK clock controller

The HFCLK clock controller provides several clocks in the system.

These are as follows:

  • HCLK: 64 MHz CPU clock
  • PCLK1M: 1 MHz peripheral clock
  • PCLK16M: 16 MHz peripheral clock
  • PCLK32M: 32 MHz peripheral clock

The HFCLK controller uses the following high frequency clock (HFCLK) sources:

  • 64 MHz oscillator (HFINT)
  • 64 MHz high accuracy oscillator (HFXO)

For illustration, see Clock and oscillator setup.

The HFCLK controller will automatically provide the clock(s) requested by the system. If the system does not request any clocks from the HFCLK controller, the controller will switch off all its clock sources and enter a power saving mode.

The HFINT source will be used when HFCLK is requested and HFXO has not been started.

The HFXO is started by triggering the HFCLKSTART task and stopped using the HFCLKSTOP task. A HFCLKSTARTED event will be generated when the HFXO has started and its frequency is stable.

LFCLK clock controller

The system supports several low frequency clock sources.

As illustrated in Clock and oscillator setup, the system supports the following low frequency clock sources:

  • LFRC: 32.768 kHz RC oscillator
  • LFXO: 32.768 kHz high accuracy oscillator

The LFCLK clock controller and all LFCLK clock sources are always switched off when in System OFF mode.

The LFCLK clock is started by first selecting the preferred clock source in the LFCLKSRC register and then triggering the LFCLKSTART task. LFXO is recommended as the LFCLK clock source.

Note: The LTE modem requires using LFXO as the LFCLK source.

Switching between LFCLK clock sources can be done without stopping the LFCLK clock. A LFCLK clock source which is running prior to triggering the LFCLKSTART task will continue to run until the selected clock source has been available. After that the clock sources will be switched. Switching between clock sources will never introduce a glitch but it will stretch a clock pulse by 0.5 to 1.0 clock cycle (i.e. will delay rising edge by 0.5 to 1.0 clock cycle).

Note: If the watchdog timer (WDT) is running, the default LFCLK clock source (LFRC - see LFCLKSRC) is started automatically (LFCLKSTART task doesn't have to be triggered).

A LFCLKSTARTED event will be generated when the selected LFCLK clock source has started.

A LFCLKSTOP task will stop global requesting of the LFCLK clock. However, if any system component (e.g. WDT, modem) requires the LFCLK, the clock won't be stopped. The LFCLKSTOP task should only be triggered after the STATE field in the LFCLKSTAT register indicates a LFCLK running-state.

32.768 kHz RC oscillator (LFRC)

The default source of the low frequency clock (LFCLK) is the 32.768 kHz RC oscillator (LFRC).

The LFRC frequency will be affected by variation in temperature.

Electrical specification

64 MHz internal oscillator (HFINT)

Symbol Description Min. Typ. Max. Units

Nominal output frequency

64 MHz

Frequency tolerance

+-1 +-5 %

Startup time

3.2 µs

64 MHz high accuracy oscillator (HFXO)

Symbol Description Min. Typ. Max. Units

Nominal output frequency

64 MHz

Frequency tolerance

+-1 ppm

Startup time

TBA ms

32.768 kHz high accuracy oscillator (LFXO)

Symbol Description Min. Typ. Max. Units


32.768 kHz

Frequency tolerance

+-20 ppm

Startup time


32.768 kHz RC oscillator (LFRC)

Symbol Description Min. Typ. Max. Units

Nominal frequency

32.768 kHz

Frequency tolerance

+-2 %

Startup time

600 µs