The user information configuration registers (UICRs) are non-volatile memory (NVM) registers for configuring user specific settings and storing secure cryptographic keys or OTP values.
The cryptographic key part of the UICR (addresses starting at 0x100 and higher) is handled by the Key Management Unit (KMU), see KMU — Key management unit for more information.
For information on writing registers, see NVMC — Non-volatile memory controller and Memory.
Base address | Domain | Peripheral | Instance | Secure mapping | DMA security | Description | Configuration | |
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0x00FF8000 | APPLICATION | UICR | UICR | S | NA |
User information configuration registers |
Register | Offset | Security | Description | |
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APPROTECT | 0x000 |
Access port protection |
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VREGHVOUT | 0x010 |
Output voltage from the high voltage (VREGH) regulator stage. The maximum output voltage from this stage is given as VDDH - VREGHDROP. |
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HFXOCNT | 0x014 |
HFXO startup counter |
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SECUREAPPROTECT | 0x01C |
Secure access port protection |
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ERASEPROTECT | 0x020 |
Erase protection |
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TINSTANCE | 0x024 |
SW-DP Target instance |
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NFCPINS | 0x028 |
Setting of pins dedicated to NFC functionality: NFC antenna or GPIO |
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OTP[n] | 0x100 |
One time programmable memory |
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KEYSLOT.CONFIG[n].DEST | 0x400 |
Destination address where content of the key value registers (KEYSLOT.KEYn.VALUE[0-3]) will be pushed by KMU. Note that this address must match that of a peripherals APB mapped write-only key registers, else the KMU can push this key value into an address range which the CPU can potentially read. |
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KEYSLOT.CONFIG[n].PERM | 0x404 |
Define permissions for the key slot. Bits 0-15 and 16-31 can only be written when equal to 0xFFFF. |
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KEYSLOT.KEY[n].VALUE[o] | 0x800 |
Define bits [31+o*32:0+o*32] of value assigned to KMU key slot. |
Address offset: 0x000
Access port protection
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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ID | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | |||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
PALL |
Blocks debugger read/write access to all CPU registers and memory mapped addresses. Using any value except Unprotected will lead to the protection being enabled. Bits with value '1' can be written to '0'. Bits with value '0' cannot be written to '1'. |
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Unprotected |
0x50FA50FA |
Unprotected |
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Protected |
0x00000000 |
Protected |
Address offset: 0x010
Output voltage from the high voltage (VREGH) regulator stage. The maximum output voltage from this stage is given as VDDH - VREGHDROP.
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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ID | A | A | A | ||||||||||||||||||||||||||||||||
Reset 0xFFFFFFFF | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
VREGHVOUT |
VREGH regulator output voltage. |
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1V8 |
0 |
1.8 V |
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2V1 |
1 |
2.1 V |
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2V4 |
2 |
2.4 V |
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2V7 |
3 |
2.7 V |
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3V0 |
4 |
3.0 V |
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3V3 |
5 |
3.3 V |
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DEFAULT |
7 |
Default voltage: 1.8 V |
Address offset: 0x014
HFXO startup counter
The CLKSTARTED events are generated after the HFXO power up time + the HFXOCNT-defined debounce time + PLL lock time has elapsed. If the HFXO has already been requested by another clock source and is already running, the CLKSTARTED event is generated as soon as the PLL has locked.
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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ID |
A |
A |
A |
A |
A |
A |
A |
A |
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Reset 0xFFFFFFFF | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
HFXOCNT |
HFXO startup counter. Total debounce time = HFXOCNT*64 us + 0.5 us |
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MinDebounceTime |
0 |
Min debounce time = (0*64 us + 0.5 us) |
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MaxDebounceTime |
254 |
Max debounce time = (254*64 us + 0.5 us) |
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DefaultDebounceTime |
255 |
Default debounce time for erased UICR = 4*64 us + 0.5 us |
Address offset: 0x01C
Secure access port protection
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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ID | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | |||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
PALL |
Blocks debugger read/write access to all secure CPU registers and secure memory mapped addresses. Using any value except Unprotected will lead to the protection being enabled. Bits with value '1' can be written to '0'. Bits with value '0' cannot be written to '1'. |
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Unprotected |
0x50FA50FA |
Unprotected |
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Protected |
0x00000000 |
Protected |
Address offset: 0x020
Erase protection
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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ID | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | |||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
PALL |
Blocks NVMC ERASEALL and CTRLAP ERASEALL functionality. Using any value except Unprotected will lead to the protection being enabled. |
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Unprotected |
0xFFFFFFFF |
Unprotected |
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Protected |
0x00000000 |
Protected |
Address offset: 0x024
SW-DP Target instance
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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ID |
A |
A |
A |
A |
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Reset 0xFFFFFFFF | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
TINSTANCE |
TINSTANCE bits are negated and used in the SW-DP DLPIDR.TINSTANCE field. E.g. 0xF in this field is translated to 0x0 in DLPIDR.TINSTANCE field. |
Address offset: 0x028
Setting of pins dedicated to NFC functionality: NFC antenna or GPIO
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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ID | A | ||||||||||||||||||||||||||||||||||
Reset 0xFFFFFFFF | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
PROTECT |
Setting of pins dedicated to NFC functionality |
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Disabled |
0 |
Operation as GPIO pins. Same protection as normal GPIO pins |
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NFC |
1 |
Operation as NFC antenna pins. Configures the protection for NFC operation |
Address offset: 0x100 + (n × 0x4)
One time programmable memory
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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ID | B | B | B | B | B | B | B | B | B | B | B | B | B | B | B | B | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | |||
Reset 0xFFFFFFFF | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW1 |
LOWER |
Lower half word Can only be written to a non 0xFFFF value once. |
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B | RW1 |
UPPER |
Upper half word Can only be written to a non 0xFFFF value once. |
Address offset: 0x400 + (n × 0x8)
Destination address where content of the key value registers (KEYSLOT.KEYn.VALUE[0-3]) will be pushed by KMU. Note that this address must match that of a peripherals APB mapped write-only key registers, else the KMU can push this key value into an address range which the CPU can potentially read.
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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ID | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | |||
Reset 0xFFFFFFFF | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
DEST |
Secure APB destination address |
Address offset: 0x404 + (n × 0x8)
Define permissions for the key slot. Bits 0-15 and 16-31 can only be written when equal to 0xFFFF.
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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ID | D | C | B | A | |||||||||||||||||||||||||||||||
Reset 0xFFFFFFFF | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
WRITE |
Write permission for key slot |
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Disabled |
0 |
Disable write to the key value registers |
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Enabled |
1 |
Enable write to the key value registers |
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B | RW |
READ |
Read permission for key slot |
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Disabled |
0 |
Disable read from key value registers |
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Enabled |
1 |
Enable read from key value registers |
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C | RW |
PUSH |
Push permission for key slot |
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Disabled |
0 |
Disable pushing of key value registers over secure APB, but can be read if field READ is Enabled |
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Enabled |
1 |
Enable pushing of key value registers over secure APB. Register KEYSLOT.CONFIGn.DEST must contain a valid destination address! |
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D | RW |
STATE |
Revocation state for the key slot Note that it is not possible to undo a key revocation by writing the value '1' to this field |
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Revoked |
0 |
Key value registers can no longer be read or pushed |
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Active |
1 |
Key value registers are readable (if enabled) and can be pushed (if enabled) |
Address offset: 0x800 + (n × 0x10) + (o × 0x4)
Define bits [31+o*32:0+o*32] of value assigned to KMU key slot.
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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ID | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | |||
Reset 0xFFFFFFFF | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |||
ID | R/W | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
VALUE |
Define bits [31+o*32:0+o*32] of value assigned to KMU key slot |