NVMC — Non-volatile memory controller

The non-volatile memory controller (NVMC) is used for writing and erasing of the internal flash memory and the UICR (user information configuration registers).

The CONFIG is used to enable the NVMC for writing (CONFIG.WEN = Wen) and erasing (CONFIG.WEN = Een).

The CPU must be halted before initiating a NVMC operation from the debug system.

Writing to flash

When write is enabled, full 32-bit words can be written to word-aligned addresses in flash memory.

As illustrated in Memory, the flash is divided into multiple pages. The same 32-bit word in flash memory can only be written n WRITE number of times before a page erase must be performed.

The NVMC is only able to write 0 to bits in flash memory that are erased (set to 1). It cannot rewrite a bit back to 1. Only full 32-bit words can be written to flash memory using the NVMC interface. To write less than 32 bits, write the data as a full 32-bit word and set all the bits that should remain unchanged in the word to 1. The restriction on the number of writes (nWRITE) still applies in this case.

Only word-aligned writes are allowed. Byte or half-word-aligned writes will result in a hard fault.

The time it takes to write a word to flash is specified by tWRITE. The CPU is halted if the CPU executes code from the flash while the NVMC is writing to the flash.

NVM writing time can be reduced by using READYNEXT. If this status bit is set to 1, code can perform the next data write to the flash. This write will be buffered and will be taken into account as soon as the ongoing write operation is completed.

Erasing a page in flash

When erase is enabled, the flash memory can be erased page by page using the ERASEPAGE.

After erasing a flash page, all bits in the page are set to 1. The time it takes to erase a page is specified by tERASEPAGE. The CPU is halted if the CPU executes code from the flash while the NVMC is writing to the flash.

See Partial erase of a page in flash for information on dividing the page erase time into shorter chunks.

Writing to user information configuration registers (UICR)

User information configuration registers (UICR) are written in the same way as flash. After UICR has been written, the new UICR configuration will only take effect after a reset.

UICR can only be written nWRITE number of times before an erase must be performed using ERASEUICR or ERASEALL. The time it takes to write a word to UICR is specified by tWRITE. The CPU is halted if the CPU executes code from the flash while the NVMC is writing to the UICR.

Erasing user information configuration registers (UICR)

When erase is enabled, UICR can be erased using the ERASEUICR.

After erasing UICR, all bits in UICR are set to 1. The time it takes to erase UICR is specified by tERASEPAGE. The CPU is halted if the CPU executes code from the flash while the NVMC performs the erase operation.

Erase all

When erase is enabled, flash and UICR can be erased completely in one operation by using the ERASEALL. This operation will not erase the factory information configuration registers (FICR).

The time it takes to perform an ERASEALL command is specified by tERASEALL. The CPU is halted if the CPU executes code from the flash while the NVMC performs the erase operation.

Access port protection behavior

When access port protection is enabled, parts of the NVMC functionality will be blocked in order to prevent intentional or unintentional erase of UICR.

Table 1. NVMC Protection
  CTRL-AP ERASEALL NVMC ERASEPAGE NVMC ERASEPAGE PARTIAL NVMC ERASEALL NVMC ERASEUICR
APPROTECT              
Disabled Allowed Allowed Allowed Allowed Allowed    
Enabled Allowed Allowed Allowed Allowed Blocked    

Partial erase of a page in flash

Partial erase is a feature in the NVMC to split a page erase time into shorter chunks to prevent longer CPU stalls in time-critical applications. Partial erase is only applicable to the code area in flash memory and does not work with UICR.

When erase is enabled, the partial erase of a flash page can be started by writing to ERASEPAGEPARTIAL. The duration of a partial erase can be configured in ERASEPAGEPARTIALCFG. A flash page is erased when its erase time reaches tERASEPAGE. Use ERASEPAGEPARTIAL N number of times so that N * ERASEPAGEPARTIALCFG ≥ tERASEPAGE, where N * ERASEPAGEPARTIALCFG gives the cumulative (total) erase time. Every time the cumulative erase time reaches tERASEPAGE, it counts as one erase cycle.

After the erase is complete, all bits in the page are set to 1. The CPU is halted if the CPU executes code from the flash while the NVMC performs the partial erase operation.

The bits in the page are undefined if the flash page erase is incomplete, i.e. if a partial erase has started but the total erase time is less than tERASEPAGE.

Cache

An instruction cache (I-Cache) can be enabled for the ICODE bus in the NVMC.

A cache hit is an instruction fetch from the cache, and it has a 0 wait-state delay. The number of wait-states for a cache miss, where the instruction is not available in the cache and needs to be fetched from flash, is shown in CPU.

Enabling the cache can increase CPU performance and reduce power consumption by reducing the number of wait cycles and the number of flash accesses. This will depend on the cache hit rate. Cache will use some current when enabled. If the reduction in average current due to reduced flash accesses is larger than the cache power requirement, the average current to execute the program code will decrease.

When disabled, the cache does not use current and does not retain its content.

It is possible to enable cache profiling to analyze the performance of the cache for your program using the ICACHECNF register. When profiling is enabled, the IHIT and IMISS registers are incremented for every instruction cache hit or miss, respectively. The hit and miss profiling registers do not wrap around after reaching the maximum value. If the maximum value is reached, consider profiling for a shorter duration to get correct numbers.

Registers

Table 2. Instances
Base address Peripheral Instance Description Configuration
0x4001E000 NVMC NVMC

Non-volatile memory controller

    
Table 3. Register overview
Register Offset Description
READY 0x400

Ready flag

  
READYNEXT 0x408

Ready flag

  
CONFIG 0x504

Configuration register

  
ERASEPAGE 0x508

Register for erasing a page in code area

  
ERASEPCR1 0x508

Register for erasing a page in code area, equivalent to ERASEPAGE

Deprecated
ERASEALL 0x50C

Register for erasing all non-volatile user memory

  
ERASEPCR0 0x510

Register for erasing a page in code area, equivalent to ERASEPAGE

Deprecated
ERASEUICR 0x514

Register for erasing user information configuration registers

  
ERASEPAGEPARTIAL 0x518

Register for partial erase of a page in code area

  
ERASEPAGEPARTIALCFG 0x51C

Register for partial erase configuration

  
ICACHECNF 0x540

I-code cache configuration register

  
IHIT 0x548

I-code cache hit counter

  
IMISS 0x54C

I-code cache miss counter

  

READY

Address offset: 0x400

Ready flag

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000001 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
ID Access Field Value ID Value Description
A R

READY

    

NVMC is ready or busy

     

Busy

0

NVMC is busy (on-going write or erase operation)

     

Ready

1

NVMC is ready

READYNEXT

Address offset: 0x408

Ready flag

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                              

A
Reset 0x00000001 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
ID Access Field Value ID Value Description
A R

READYNEXT

    

NVMC can accept a new write operation

     

Busy

0

NVMC cannot accept any write operation

     

Ready

1

NVMC is ready

CONFIG

Address offset: 0x504

Configuration register

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                         A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

WEN

    

Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used.

Enabling write or erase will invalidate the cache and keep it invalidated.

     

Ren

0

Read only access

     

Wen

1

Write enabled

     

Een

2

Erase enabled

ERASEPAGE

Address offset: 0x508

Register for erasing a page in code area

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

ERASEPAGE

    

Register for starting erase of a page in code area

The value is the address to the page to be erased. (Addresses of first word in page). The erase must be enabled using CONFIG.WEN before the page can be erased. Attempts to erase pages that are outside the code area may result in undesirable behavior, e.g. the wrong page may be erased.

ERASEPCR1 ( Deprecated )

Address offset: 0x508

Register for erasing a page in code area, equivalent to ERASEPAGE

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

ERASEPCR1

    

Register for erasing a page in code area, equivalent to ERASEPAGE

ERASEALL

Address offset: 0x50C

Register for erasing all non-volatile user memory

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

ERASEALL

    

Erase all non-volatile memory including UICR registers. The erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased.

     

NoOperation

0

No operation

     

Erase

1

Start chip erase

ERASEPCR0 ( Deprecated )

Address offset: 0x510

Register for erasing a page in code area, equivalent to ERASEPAGE

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

ERASEPCR0

    

Register for starting erase of a page in code area, equivalent to ERASEPAGE

ERASEUICR

Address offset: 0x514

Register for erasing user information configuration registers

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

ERASEUICR

    

Register starting erase of all user information configuration registers. The erase must be enabled using CONFIG.WEN before the UICR can be erased.

     

NoOperation

0

No operation

     

Erase

1

Start erase of UICR

ERASEPAGEPARTIAL

Address offset: 0x518

Register for partial erase of a page in code area

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

ERASEPAGEPARTIAL

    

Register for starting partial erase of a page in code area

The value is the address to the page to be partially erased (address of the first word in page). The erase must be enabled using CONFIG.WEN before every erase page partial and disabled using CONFIG.WEN after every erase page partial. Attempts to erase pages that are outside the code area may result in undesirable behavior, e.g. the wrong page may be erased.

ERASEPAGEPARTIALCFG

Address offset: 0x51C

Register for partial erase configuration

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                  

A

A

A

A

A

A

A
Reset 0x0000000A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0
ID Access Field Value ID Value Description
A RW

DURATION

    

Duration of the partial erase in milliseconds

The user must ensure that the total erase time is long enough for a complete erase of the flash page.

ICACHECNF

Address offset: 0x540

I-code cache configuration register

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                              

B

              

A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

CACHEEN

    

Cache enable

     

Disabled

0

Disable cache. Invalidates all cache entries.

     

Enabled

1

Enable cache

B RW

CACHEPROFEN

    

Cache profiling enable

     

Disabled

0

Disable cache profiling

     

Enabled

1

Enable cache profiling

IHIT

Address offset: 0x548

I-code cache hit counter

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

HITS

    

Number of cache hits.

Register is writable, but only to '0'.

IMISS

Address offset: 0x54C

I-code cache miss counter

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

MISSES

    

Number of cache misses.

Register is writable, but only to '0'.

Electrical specification

Flash programming

Symbol Description Min. Typ. Max. Units
nWRITE

Number of times a 32-bit word can be written before erase

 2  
nENDURANCE

Erase cycles per page

 10000  
tWRITE

Time to write one 32-bit word

 411 µs
tERASEPAGE

Time to erase one page

 851 ms
tERASEALL

Time to erase all flash

 1691 ms
tERASEPAGEPARTIAL,acc

Accuracy of the partial page erase duration. Total execution time for one partial page erase is defined as ERASEPAGEPARTIALCFG * tERASEPAGEPARTIAL,acc.

 1.051  

Cache size

Symbol Description Min. Typ. Max. Units
SizeICODE

I-Code cache size

 2048 Bytes
1 Applies when HFXO is used. Timing varies according to HFINT accuracy when HFINT is used.