The ARM® Cortex®-M4 processor with floating-point unit (FPU) has a 32-bit instruction set (Thumb®-2 technology) that implements a superset of 16- and 32-bit instructions to maximize code density and performance.
This processor implements the following features that enable energy-efficient arithmetic and high-performance signal processing.
The ARM® Cortex® Microcontroller Software Interface Standard (CMSIS) hardware abstraction layer for the ARM®Cortex® processor series is implemented and available for the M4 CPU.
Real-time execution is highly deterministic in thread mode, to and from sleep modes, and when handling events at configurable priority levels via the nested vectored interrupt controller (NVIC).
Executing code from flash memory will have a wait state penalty on the nRF52 Series. An instruction cache can be enabled to minimize flash wait states when fetching instructions. For more information on cache, see Cache. The Electrical specification shows CPU performance parameters including wait states in different modes, CPU current and efficiency, and processing power and efficiency based on the CoreMark® benchmark.
The ARM system timer (SysTick) is present on nRF52840. The SysTick's clock will only tick when the CPU is running or when the system is in debug interface mode.
The floating point unit (FPU) may generate exceptions when used due to e.g. overflow or underflow, which in turn will trigger the FPU interrupt.
See Instantiation for more information about the exceptions triggering the FPU interrupt.
To clear the IRQ (interrupt request) line when an exception has occurred, the relevant exception bit within the floating-point status and control register (FPSCR) needs to be cleared. For more information about the FPSCR or other FPU registers, see Cortex-M4 Devices Generic User Guide.
The ARM® Cortex®-M4 processor has a number of CPU options and support modules implemented on the IC.
| Option / Module | Description | Implemented |
|---|---|---|
| Core options | ||
| NVIC | Nested vector interrupt controller | 48 vectors |
| PRIORITIES | Priority bits | 3 |
| WIC | Wakeup interrupt controller | NO |
| Endianness | Memory system endianness | Little endian |
| Bit-banding | Bit banded memory | NO |
| DWT | Data watchpoint and trace | YES |
| SysTick | System tick timer | YES |
| Modules | ||
| MPU | Memory protection unit | YES |
| FPU | Floating-point unit | YES |
| DAP | Debug access port | YES |
| ETM | Embedded trace macrocell | YES |
| ITM | Instrumentation trace macrocell | YES |
| TPIU | Trace port interface unit | YES |
| ETB | Embedded trace buffer | NO |
| FPB | Flash patch and breakpoint unit | YES |
| HTM | AMBA™ AHB trace macrocell | NO |
The CPU clock speed is 64 MHz. Current and efficiency data is taken when in System ON and the CPU is executing the CoreMark® benchmark. It includes power regulator and clock base currents. All other blocks are IDLE.
| Symbol | Description | Min. | Typ. | Max. | Units | ||||
|---|---|---|---|---|---|---|---|---|---|
| WFLASH |
CPU wait states, running CoreMark from flash, cache disabled |
2 | |||||||
| WFLASHCACHE |
CPU wait states, running CoreMark from flash, cache enabled |
3 | |||||||
| WRAM |
CPU wait states, running CoreMark from RAM |
0 | |||||||
| CMFLASH |
CoreMark, running CoreMark from flash, cache enabled |
212 | CoreMark | ||||||
| CMFLASH/MHz |
CoreMark per MHz, running CoreMark from flash, cache enabled |
3.3 | CoreMark/MHz | ||||||
| CMFLASH/mA |
CoreMark per mA, running CoreMark from flash, cache enabled, DCDC 3V |
64 | CoreMark/mA |