SYSTEM features complement the power supply. Thermal protection can be enabled and set to provide a warning interrupt when the die temperature is too high. In the case of extreme temperature, the chip shuts down to prevent damage.
A watchdog timer can be set to provide a reset to the host if firmware is unresponsive.
Hibernate mode is the lowest power operating mode of the chip. It reduces the quiescent current of the device to extend battery life. The device will automatically wake-up after a pre-configured timeout.
Three general purpose I/Os are available and can be configured to control off-chip sensors or power supplies.
Thermal protection prevents permanent damage to the chip and provides a warning to the host system when the chip overheats. It is enabled and configured through TWI.
Thermal protection monitors the on-chip temperature sensor element. When in an active power mode with an expected high current load, thermal protection must be enabled through registers to save power. An example is when BUCK is running in PWM mode. Register TH.DYN.POWERUP configures the thermal sensor and selects which BUCK will activate the thermal sensor during PWM mode.
During startup, thermal protection is always enabled with TLOW_RISE and TLOW_FALL thresholds. If the temperature is higher than TLOW_RISE, startup is halted until the temperature falls below TLOW_FALL.
When startup is complete and the READY pin is set, the temperature thresholds are changed to THIGH_RISE and THIGH_FALL. Thermal warning and thermal shutdown are disabled by default after startup.
Thermal warning must be enabled in register INTENSET0 for the device to send an interrupt to the host system when the chip temperature rises over THIGH_RISE.
Thermal shutdown must be enabled separately for the device to shutdown when the temperature rises above TSHUTDOWN. The device starts up again once the die cools down.
| Symbol | Description | Min. | Typ. | Max. | Units |
|---|---|---|---|---|---|
| TSHUTDOWN | Shutdown threshold temperature | 140 | C | ||
| THIGH_RISE | Rising temperature threshold in normal operation | 115 | C | ||
| THIGH_FALL | Falling temperature threshold in normal operation | 107 | C | ||
| TLOW_RISE | Rising temperature threshold in startup | 107 | C | ||
| TLOW_FALL | Falling temperature threshold in startup | 102 | C |
The watchdog timer generates a reset when the system is stalled and no internal watchdog is running during sleep.
By default, the watchdog is disabled after startup. The watchdog is configured and enabled through TWI. Once enabled, the watchdog uses the 2 kHz clock as a counter. The value for the watchdog trigger target can be programmed from 4 seconds up to 776.7 days in 4 second intervals. The watchdog and wakeup timer share the same counter, but only one timer can be active at a time.
When the watchdog is configured and enabled, the host periodically resets the counter before it reaches the trigger value. If the host is not able to reset the counter, the watchdog will reach the trigger value. The device will pull down the READY pin and reset, including the watchdog. After this reset and power cycle, the device then starts up again.
| WDTRIGGERVALUE[23:0] | Programmed time |
|---|---|
| 24’h000000 | Initialization value (do not use) |
| 24’h000001 | 0 s (do not use) |
| 24’h000002 | 4 s |
| 24’h000003 | 8 s |
| ... | ... |
| 24’hFFFFFD | ~776.7 d – 4 s |
| 24’hFFFFFE | ~776.7 d |
| 24’hFFFFFF | ~776.7 d + 4 s |
Hibernate mode is configured, started, and controlled through the TWI. It is the lowest power mode and uses only 200 nA.
The device enters Hibernate mode by configuring the watchdog and writing to register WD.REQ.POWERDOWN. All BUCKs are turned off and the device enters a low power state. The TWI is not accessible from software during Hibernate mode.
The oscillator and timer circuits are the only components active in this mode. The ENABLE pin must be connected to VIN. The watchdog timer must be configured as a wake up source before entering this mode. The device powers up after the timer expires.
The wakeup timer can be programmed from 4 seconds up to 776.7 days in 4 second intervals, see Trigger values for the watchdog and wakeup timers.
When the wakeup timer reaches its target value, the device powers up.
The chip starts up when ENABLE is pulled to VIN. Pulling down ENABLE shuts down the device, resets all registers and reduces power consumption from VIN supply. See Electrical specification CMOS mode for more information.
The READY pin is an open-drain pin. Logic HIGH on READY means that the device has started up (all BUCK regulators are on) and is ready for use. Ready goes LOW when the device shuts down. See Electrical specification CMOS mode for more information.
Device control is managed through an I2C compatible TWI serial interface and registers on the chip. The device has a serial data I/O signal SDA and a clock input signal SCL. The VDD_TWI pin supplies 1.8 V to the TWI. The startup sequence activates TWI when READY is HIGH. TWI configures SDA pin output drive strength through register PADDRIVESTRENGTH[5].
TWI configures and controls the thermal sensor, regulators, watchdog, and wakeup timer functions. The values found in Electrical specification Schmitt trigger mode apply to SDA and SCL pins. The pins are referenced to VDDTWI level.
nINT is an active LOW, open drain interrupt pin. The TWI interface configures, reads, and clears nINT.
BUCK_MODE[n] pins toggle the power mode for BUCK[n]. Register SWREADY must be written to enable the pins. BUCK_MODE[n] pins are configured as Schmitt trigger inputs by default, see Electrical specification Schmitt trigger mode. CMOS input is also available, see Electrical specification CMOS mode.
BUCK0 is forced to PWM mode by default when BUCKMODE0 or BUCKMODE1 input is HIGH and SWREADY=1. BUCK1 and BUCK2 use the BUCKMODE1 input pin state. BUCK3 uses the BUCKMODE2 input pin state.
BUCK_MODE[n] pins use VO2 when configured to Schmitt trigger mode. When in CMOS mode, VIN is used as reference. See Electrical specification CMOS mode for more information.
GPIO[n] are general purpose input/output pins that are available to the host. After startup, the GPIO[n] pins are disabled and set to high-impedance mode by default. The dedicated pin supply, VIN_GPIO, must be connected to VIN.
The pins are set to VINGPIO when used in CMOS mode, see Electrical specification CMOS mode. In Schmitt trigger mode, the pins are set to VO2. See Electrical specification Schmitt trigger mode for more information about GPIO[n] pins.
This chapter describes the electrical specifications for I/Os.
This section is valid for ENABLE, READY, nINT, SCL, SDA, GPIO[n], and BUCK_MODE[n] pins when put in CMOS mode.
| Symbol | Description | Min. | Typ. | Max. | Units |
|---|---|---|---|---|---|
| VIO | I/O driver power supply (VIN,
VIN_GPIO) I/O driver power supply for the TWI (VDD_TWI) I/O driver supply for open-drain pins READY and nINT (VO0_IN) |
3.0 1.62 1.62 |
5.5 1.95 3.47 |
V | |
| VIL | Input low voltage | 0.18VIO | V | ||
| VIH | Input high voltage | 0.89VIO | V | ||
| VOL | Output low voltage | 0.55VIO | V | ||
| VOH | Output high voltage | 0.62VIO | V | ||
| IOL,5V,LS | Output current, normal strength, VIO=5 V | 4.4 | mA | ||
| IOL,5V,HS | IOL output current, high strength, VIO=5 V | 18 | mA | ||
| IOH,5V,LS | IOH output current, normal strength, VIO=5 V | 8 | mA | ||
| IOH,5V,HS | IOH output current, high strength, VIO=5 V | 29 | mA | ||
| RPU,5V | I/O pull-up resistor, when enabled VIO=5 V | 50 | 77 | 132 | kΩ |
| RPD,5V | I/O pull-down resistor, when enabled VIO=5 V | 58 | 99 | 213 | kΩ |
| IOL,3V3,LS | Output current, normal strength, VIO=3.3 V | 3 | mA | ||
| IOL,3V3,HS | Output current, high strength, VIO=3.3 V | 13 | mA | ||
| IOH,3V3,LS | Output current, normal strength, VIO=3.3 V | 4.5 | mA | ||
| IOH,3V3,HS | Output current,high strength, VIO=3.3 V | 17 | mA | ||
| RPU,3V3 | I/O pull-up resistor, when enabled, VIO=3.3 V | 76 | 124 | 219 | kΩ |
| RPD,3V3 | I/O pull-down resistor, when enabled VIO=3.3 V | 92 | 173 | 382 | kΩ |
| IOL,2V5,LS | Output current, normal strength, VIO=2.5 V | 3.2 | mA | ||
| IOL,2V5,HS | Output current, high strength, VIO=2.5 V | 13 | mA | ||
| IOH,2V5,LS | Output current, normal strength, VIO=2.5 V | 2.7 | mA | ||
| IOH,2V5,HS | Output current, high strength, VIO=2.5 V | 10 | mA | ||
| RPU,2V5 | I/O pull-up resistor, when enabled VIO=2.5 V | 150 | 181 | 333 | kΩ |
| RPD,2V5 | I/O pull-down resistor, when enabled VIO=2.5 V | 139 | 278 | 626 | kΩ |
| IOL,1V8,LS | Output current, normal strength, VIO=1.8 V | 1.4 | mA | ||
| IOL,1V8,HS | Output current, high strength, VIO=1.8 V | 5.5 | mA | ||
| IOH,1V8,LS | Output current, normal strength, VIO=1.8 V | 1.1 | mA | ||
| IOH,1V8,HS | Output current, high strength, VIO=1.8 V | 4 | mA | ||
| RPU,1V8 | I/O pull-up resistor, when enabled VIO=1.8 V | 173 | 321 | 604 | kΩ |
| RPD,1V8 | I/O pull-down resistor, when enabled VIO=1.8 V | 266 | 570 | 1277 | kΩ |
This section is valid for BUCK_MODE[n] and GPIO[n] pins when they are configured as Schmitt trigger inputs.
| Symbol | Description | Min. | Typ. | Max. | Units |
|---|---|---|---|---|---|
| VTPOS | Positive going input voltage threshold (VO2=1.2 V) | 0.7 | 0.9 | V | |
| VTNEG | Negative going input voltage threshold (VO2=1.2 V) | 0.35 | 0.65 | V | |
| DVT | Hysteresis (VTPOS - VTNEG) (VO2=1.2 V) | 0.3 | V |