The SHPHLD pin is a reset control, in addition to being used for exiting Ship and Hibernate mode.
The SHPHLD pin has an internal pull-up resistor RSHPHLD to VBAT. The functionality of the pin is determined by the device mode.
If configured, a short logic-low pulse on SHPHLD sends an interrupt to the host. Host software reads the pin state in register SHPHLDSTATUS.
A long logic-low (> tRESETBUT ) on SHPHLD causes a power cycle and resets the whole system. This feature is enabled by default after power-up, but can be disabled by the host software. See register LPRESETCONFIG for more information.
When a logic-low occurs for longer than tshipToActive, the device wakes up from Ship or Hibernate mode, performs an internal reset, and transitions to normal operation.
A two-button reset is implemented by connecting one button to the SHPHLD pin and another button to GPIO0. This feature must be enabled by host software in LPRESETCONFIG. Pressing and holding both buttons for longer than tRESETBUT initiates a logic-low and starts a power cycle.
Host software can reset the device by writing the TASKSWRESET bit in register TASKSWRESET. As a consequence, a power cycle is performed. A reset is not possible in Ship or Hibernate mode.
Only POR and TASKCLRERRLOG can initialize the context registers found at SCRATCH[n]. The cause of the first reset is reported in register RSTCAUSE.