npm1300

Reset and error registers

This section details the error and reset related registers.

Note: During the cooling period after a TSD and if VSYS drops below VSYSCOMP, VSYSLOW could be set instead of THERMALSHUTDOWN in register RSTCAUSE.

Registers

Instances

Instance Base address Description
ERRLOG 0x00000E00

Error Log registers

ERRLOG register map

Register overview

Register Offset Description
TASKCLRERRLOG 0x0

task to clear the Errlog registers

SCRATCH0 0x1

Scratch register 0

SCRATCH1 0x2

Scratch register 1

RSTCAUSE 0x3

Error log for internal reset causes. Cleared withTASK_CLR_ERRLOG

CHARGERERRREASON 0x4

Error log for slowDomain. Cleared with TASK_CLR_ERRLOG

CHARGERERRSENSOR 0x5

Bcharger Fsm sensor error. Cleared with TASK_CLR_ERRLOG

TASKCLRERRLOG

Address offset: 0x0

task to clear the Errlog registers

Bit number 7 6 5 4 3 2 1 0
ID               A
Reset 0x00 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

W

TASKCLRERRLOG

 

Clear Errlog

SCRATCH0

Address offset: 0x1

Scratch register 0

Bit number 7 6 5 4 3 2 1 0
ID B B B B B B B A
Reset 0x00 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

BOOTTIMEREN

 

Enable Boot Monitor Timer, only cleared by POR

     

NOBOOTMON

0

bootMonitor disable

     

BOOTMON

1

bootMonitor enable

B

RW

SCRATCH0

 

scratch register, only cleared by POR

SCRATCH1

Address offset: 0x2

Scratch register 1

Bit number 7 6 5 4 3 2 1 0
ID A A A A A A A A
Reset 0x00 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

SCRATCH1

 

scratch register, only cleared by POR

RSTCAUSE

Address offset: 0x3

Error log for internal reset causes. Cleared withTASK_CLR_ERRLOG

Bit number 7 6 5 4 3 2 1 0
ID   G F E D C B A
Reset 0x00 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

R

SHIPMODEEXIT

 

internal reset caused by shipmode exit

     

NORST

0

no shipmode reset

     

RST

1

reset activated by shipmode exit

B

R

BOOTMONITORTIMEOUT

 

internal reset caused by boot monitor timeout

     

NORST

0

no bootMonitor reset

     

RST

1

reset activated by bootMonitor

C

R

WATCHDOGTIMEOUT

 

internal reset caused by watchdog timeout

     

NORST

0

no watchdog reset

     

RST

1

reset activated by watchdog

D

R

LONGPRESSTIMEOUT

 

internal reset caused by shphld long press

     

NORST

0

no long press reset

     

RST

1

Reset activated by long press of SHPHLD or SHPHLD+GPIO

E

R

THERMALSHUTDOWN

 

internal reset caused by TSD

     

NORST

0

no TSD reset

     

RST

1

reset activated by TSD

F

R

VSYSLOW

 

internal reset caused by POF, VSYS low

     

NORST

0

no VSYS low reset

     

RST

1

reset activated by VSYS low

G

R

SWRESET

 

internal reset caused by soft reset

     

NORST

0

no s/w reset

     

RST

1

reset activated by s/w reset

CHARGERERRREASON

Address offset: 0x4

Error log for slowDomain. Cleared with TASK_CLR_ERRLOG

Bit number 7 6 5 4 3 2 1 0
ID   G F E D C B A
Reset 0x00 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

R

NTCSENSORERR

 

NTC thermistor sensor error

B

R

VBATSENSORERR

 

VBAT Sensor Error

C

R

VBATLOW

 

VBAT Low Error

D

R

VTRICKLE

 

Vtrickle Error

E

R

MEASTIMEOUT

 

Measurement Timeout Error

F

R

CHARGETIMEOUT

 

Charge Timeout Error

G

R

TRICKLETIMEOUT

 

Trickle Timeout Error

CHARGERERRSENSOR

Address offset: 0x5

Bcharger Fsm sensor error. Cleared with TASK_CLR_ERRLOG

Bit number 7 6 5 4 3 2 1 0
ID H G F E D C B A
Reset 0x00 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

R

SENSORNTCCOLD

 

NTC thermistor Cold sensor value during error

B

R

SENSORNTCCOOL

 

NTC thermistor Cool sensor value during error

C

R

SENSORNTCWARM

 

NTC thermistor Warm sensor value during error

D

R

SENSORNTCHOT

 

NTC thermistor Hot sensor value during error

E

R

SENSORVTERM

 

Vterm sensor value during error

F

R

SENSORRECHARGE

 

Recharge sensor value during error

G

R

SENSORVTRICKLE

 

Vtrickle sensor value during error

H

R

SENSORVBATLOW

 

VbatLow sensor value during error