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POF — Power-fail comparator

The power-fail comparator (POF) provides the host with an early warning of an impending power supply failure.

POF is generated from an always active comparator monitoring the voltage on the VSYS pin. It can be configured through POFCONFIG to give a warning through a GPIO to the host.

If voltage on the VSYS pin drops below VSYSCOMP, but voltage remains above the respective BOR threshold on the VBAT or VBUS pins, the VSYS pin is disabled after tPOFWAIT and registers are reset after tPWRDN. If VSYS > VSYSCOMP, the chip powers up after tPWRDN. See Power fail warning.

Note: Before setting VSYSPOF, voltage on the VSYS pin must be higher than the selected threshold or it triggers a POF event and resets the device. VSYSPOF must be set to a higher voltage than the battery undervoltage protection level to avoid triggering the protection circuit. The POF threshold is also reset to the default setting. When VBAT > VSYSCOMP, BUCK may start up again depending on VSET[n] pin configuration.

A warning is issued in the following cases:

Figure 1. Power fail warning
Power fail warning
Figure 2. Power removal
Power removal

To use the POF warning feature, set POFWARNPOLARITY and POFENA to 1 in register POFCONFIG. GPIO settings are located in GPIO — General purpose input/output.

Electrical specification

Table 1. POF electrical specification
Symbol Description Min. Typ. Max. Unit
POF

VSYSPOF rising threshold, default

Always 100 mV (typ.) above the falling threshold

  2.9   V
VSYSPOF Minimum setting VSYSPOF falling threshold   2.6   V
VSYSPOF Default setting VSYSPOF falling threshold   2.8   V
VSYSPOF Maximum setting VSYSPOF falling threshold   3.5   V
tPOF Reaction time (from crossing the threshold to edge on the warning signal)   1   ms
tPWRDN Time in power-down mode   100   ms
tPOFWAIT Delay before enabling the active output capacitor discharge and disconnecting VBAT and VBUS from VSYS   30   ms

Registers

Instances

Instance Base address Description
POF 0x00000900

POF registers

POF register map

Register overview

Register Offset Description
POFCONFIG 0x0

Power Failure Detection block configuration

POFCONFIG

Address offset: 0x0

Power Failure Detection block configuration

Bit number 7 6 5 4 3 2 1 0
ID     C C C C B A
Reset 0x00 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

POFENA

 

Enable Power Failure feature

     

OFF

0

Off

     

ENABLED

1

WarningEnabled

B

RW

POFWARNPOLARITY

 

Power Failure Warning polarity

     

LOACTIVE

0

Active Low

     

HIACTIVE

1

Active Hi

C

RW

POFVSYSTHRESHSEL

 

VSYS Comparator Threshold Select

     

2V8

0

2.8V

     

2V6

1

2.6V

     

2V7

2

2.7V

     

2V9

3

2.9V

     

3V0

4

3.0V

     

3V1

5

3.1V

     

3V2

6

3.2V

     

3V3

7

3.3V

     

3V4

8

3.4V

     

3V5

9

3.5V

     

unused10

10

set to 2.8V

     

unused11

11

set to 2.8V

     

unused12

12

set to 2.8V

     

unused13

13

set to 2.8V

     

unused14

14

set to 2.8V

     

unused15

15

set to 2.8V