Change log

See the following list for an overview of changes from previous versions of this document.

Version Date Change
nRF9160 Engineering A v1.2 28.05.2019
  • Updated: No. 14. “Supply regulators default to LDO mode after reset”
  • Added: No. 20. “RAM content cannot be trusted upon waking up from System ON IDLE or System OFF mode”
  • Added: No. 21. “Disabling instruction cache causes skip of next instruction”
nRF9160 Engineering A v1.1 10.01.2019
  • Added: No. 17. “LTE modem stops when debugging through SWD interface”
nRF9160 Engineering A v1.0 12.12.2018
  • Added: No. 1. “Excessive power consumption after using STOP task”
  • Added: No. 2. “CPU code execution from RAM halted during flash page erase operation”
  • Added: No. 4. “Bits in GPIO LATCH register are incorrectly set to 1”
  • Added: No. 6. “SLEEPENTER and SLEEPEXIT events asserted after pin reset”
  • Added: No. 7. “Subsequent accesses between info_mem and main_mem of the flash may not work properly”
  • Added: No. 8. “Reduced SFDR”
  • Added: No. 10. “MAGPIO and MIPI RFFE - high initial voltage”
  • Added: No. 12. “SWD debugger scan”
  • Added: No. 14. “LDO mode at startup”
  • Added: No. 16. “SAADC result”