[6] NVMC: Disabling instruction cache causes skip of next instruction

This anomaly applies to IC Rev. Rev 1, build codes QKAA-D00.

It was inherited from the previous IC revision Engineering D.

Domains

Network

Symptoms

The CPU skips the first instruction after instruction cache is disabled.

Conditions

The code executes instructions to disable the instruction cache.

Consequences

The program does not execute as expected.

Workaround

Use the following function to disable instruction cache:


_attribute_((aligned(ICACHE_LINE_SIZE)))

void icache_disable(void) {
    int key = DisableInterrupts();
    __ISB();
    NRF_NVMC->ICACHECNF = 0;
    __ISB();
    EnableInterrupts(key);
}