Errata nRF5340 - REGULATORS: VREGMAIN can malfunction in LDO mode

This anomaly applies to Revision 1, build codes CLAA-D00, QKAA-D00.

Domains

Application

Device behaves erratically.

Device is in a state where the following conditions apply:

VREGMAIN is in LDO mode.
Application core register HFCLKCTRL is not set to Div1, which means that the core is not running at 128 MHz.
Application core register HFCLK192MCTRL is not set to Div1, which means that the scalable 192 MHz clock for QSPI is not running at 192 MHz.
USBD is disabled.
SAADC is disabled.
Application core CPU is entering or exiting sleep mode (WFI/WFE).

Application core CPU can hard-fault, trigger lockup reset, or become unresponsive. Application core can behave erratically.

If using VREGMAIN in LDO mode, apply the following code after any application core reset:


*((volatile uint32_t *)0x50300C00) = 0x00009375ul;
*((volatile uint32_t *)0x503000E4) = 0x0ul;
*((volatile uint32_t *)0x50300C00) = 0x00009375ul;

The workaround has the following effect on the electrical parameters specified in the nRF5340 Product Specification v1.3:

Table 1. Affected electrical parameters in nRF5340 Product Specification v1.3
Symbol	Description	Typical value in Product Specification	Typical value after workaround	Unit
I_{ON_IDLE1,LDO}	System ON, 0k application RAM, wake on any event, regulator = LDO	3.3	105	μA
I_{ON_IDLE2,LDO}	System ON, wake on any event, regulator = LDO	3.4	105
I_PWM,RUN1,LDO	PWM running at 16 MHz, top = 10, duty = 50%; regulator = LDO	1035	1410
I_TIMER2,LDO	One TIMER running @ 16 MHz; regulator = LDO	1040	1300
I_TIMER3,LDO	One TIMER running @ 16 MHz, clock = HFXO64M; regulator = LDO	1280	1540
I_WDT,APP,LDO	Application MCU WDT started; regulator = LDO	4.9	110
I_{USB,SUSPEND,VDDH,LDO}	Current from VDDH supply (high voltage mode), VDD=3 V (VREGH output), all RAM retained, CPU sleeping, USB suspended, regulator = LDO	125	210