[119] GPIO: Writes to LATCH register take several CPU cycles to take effect

This anomaly applies to IC Rev. Rev 1, build codes QKAA-D00.

It was inherited from the previous IC revision Engineering D.

Domains

Network

Symptoms

A bit in the LATCH register reads '1' even after clearing it by writing '1'.

Conditions

Reading the LATCH register right after writing to it.

Consequences

Old value of the LATCH register is read.

Workaround

Have at least 4 CPU cycles of delay between the write and the subsequent read to the LATCH register. This can be achieved by having 4 dummy reads of the LATCH register.