Change log

See the following list for an overview of changes from previous versions of this document.

Version Date Change
nRF5340 Engineering A v1.2 28.05.2020
  • Updated: No. 42. “Reset value of HFCLKCTRL is invalid”
  • Updated: No. 53. “Current consumption in normal voltage mode is higher in System ON idle”
  • Added: No. 1. “VREGH short circuit protection is not functional”
  • Added: No. 2. “Accessing external QSPI memory without configuring QSPI makes application core unresponsive”
  • Added: No. 31. “Multidrop serial wire debug is not functional”
  • Added: No. 34. “Erase all is not functional with APPROTECT enabled”
  • Added: No. 36. “Excessive power consumption after using I2S STOP task”
  • Added: No. 52. “RAM block is not writable immediately on power-up”
  • Added: No. 66. “P1.PIN_CNF[2-3], P0.PIN_CNF[8-18] DRIVE cannot be set in some configurations”
  • Added: No. 67. “ESD HBM is less than 2 kV”
  • Added: No. 70. “Event FIELDDETECTED may be generated too early”
  • Added: No. 71. “Frame delay timing is too short after SLP_REQ”
  • Added: No. 75. “False SEQEND[0] and SEQEND[1] events are generated”
  • Added: No. 76. “Non-secure code can detect secure events”
  • Added: No. 77. “Debug power-up request is not acknowledged”
  • Added: No. 85. “Reading or executing from flash memory can lead to errors when scaling frequency”
  • Added: No. 86. “EVENTS_DONE is not functional”
  • Added: No. 87. “RSSI parameter adjustment”
  • Added: No. 90. “PIN_CNF[n] MCUSEL is reset by application core soft reset”
  • Added: No. 91. “Ramp-up is slower than specified”
  • Added: No. 93. “Writing to flash requires high voltage on VREGRADIO”
  • Added: No. 95. “VREGRADIO DC/DC can malfunction”
  • Added: No. 97. “ERASEPROTECT or APPROTECT is occasionally enabled or device startup may fail”
  • Added: No. 103. “Network core executing code from application core flash causes bus fault”
  • Added: No. 105. “Peripheral has higher than expected current consumption”
  • Added: No. 106. “SPIM4 is not functional with GPIO.PIN_CNF[n].MCUSEL configured as Peripheral”
  • Added: No. 109. “LATENCY register is not functional”
  • Added: No. 110. “QSPI is not functional with GPIO.PIN_CNF[n].MCUSEL configured as Peripheral”
  • Added: No. 113. “Reading DTX in MODECNF0 gives incorrect value”
  • Added: No. 114. “Accessing application core flash causes processor to become unresponsive”
  • Added: No. 115. “Peripheral cannot do DMA transfers from flash when application core processor is sleeping”
  • Added: No. 116. “Device spurious emission during transmit is higher than expected”
nRF5340 Engineering A v1.1 09.12.2019
  • Updated: No. 42. “Reset value of HFCLKCTRL is invalid”
  • Updated: No. 59. “QDEC is not functional”
  • Added: No. 43. “Reading QSPI registers after XIP might halt application CPU”
  • Added: No. 62. “HFXOCNT register is not functional”
  • Added: No. 64. “VREGMAIN has invalid configuration when CPU is running”
  • Added: No. 73. “ONESHOTEN[n] registers are located at an incorrect address offset”
  • Added: No. 74. “COMPARE[i]_STOP is located at an incorrect bit number in the SHORTS register”
  • Added: No. 79. “QDEC1 is not functional”
  • Added: No. 80. “PWM3 is not functional”
  • Added: No. 81. “SPIM2 and SPIM3 are not functional”
  • Added: No. 82. “TWIM2 and TWIM3 are not functional”
  • Added: No. 83. “SPIS2 and SPIS3 are not functional”
  • Added: No. 84. “UARTE2 and UARTE3 are not functional”
nRF5340 Engineering A v1.0 14.11.2019
  • Added: No. 3. “VDDHDIV5 is not functional”
  • Added: No. 4. “Changing application core frequency register HFCLKCTRL requires additional register initialization”
  • Added: No. 5. “Trace is not functional when application core is running at 128 MHz”
  • Added: No. 6. “Disabling instruction cache causes skip of next instruction”
  • Added: No. 7. “USBD is not functional”
  • Added: No. 8. “WDT1 is not functional”
  • Added: No. 9. “TPIU is missing from ROM table”
  • Added: No. 10. “Reading CNFPTR, INPTR, OUTPTR, and SCRATCHPTR pointers returns incorrect address”
  • Added: No. 11. “Reading ACL[n].ADDR returns incorrect address”
  • Added: No. 12. “SCKFREQ is not functional at 96 MHz”
  • Added: No. 13. “Bits in LATCH register are incorrectly set to 1”
  • Added: No. 14. “CC[6] and CC[7] are not functional”
  • Added: No. 15. “Odd parity setting is not functional”
  • Added: No. 16. “POWER register is not functional”
  • Added: No. 18. “32-bit sample widths and 8-bit sample in a 16-bit half-frame are not functional”
  • Added: No. 19. “Flash memory space is divided into 32 regions of 32 KiB”
  • Added: No. 20. “TASKS_CAPTURE[n], SUBSCRIBE_CAPTURE[n], and SHORTS registers are not functional”
  • Added: No. 21. “1000 kbps baud rate is not functional”
  • Added: No. 22. “CPULOCK register is not functional”
  • Added: No. 23. “Events are not generated when switching from scan mode to no-scan mode with BURST enabled”
  • Added: No. 26. “APPROTECT.DISABLE and SECUREAPPROTECT.DISABLE registers are not functional”
  • Added: No. 27. “STATUS register is not functional”
  • Added: No. 28. “INTEN register is not functional”
  • Added: No. 29. “SWIRQ is not functional”
  • Added: No. 30. “LCTRLAP field in RESETREAS register is not functional”
  • Added: No. 32. “GPIO pins assigned to network core do not retain their state in System OFF mode”
  • Added: No. 33. “LFRC frequency starts drifting even if calibration task is triggered”
  • Added: No. 37. “First clock pulse after clock stretching may be too long or too short”
  • Added: No. 42. “Reset value of HFCLKCTRL is invalid”
  • Added: No. 44. “TASKS_RESUME impacts UARTE”
  • Added: No. 45. “Receive is not functional at 32 Mbps”
  • Added: No. 46. “LFRC has higher current consumption”
  • Added: No. 47. “I2C timing spec is violated at 400 kHz”
  • Added: No. 49. “SLEEPENTER and SLEEPEXIT events are asserted after pin reset”
  • Added: No. 50. “Arm TrustZone region numbers for FICR, UICR, CACHEINFO, and CACHEDATA are incorrect”
  • Added: No. 51. “Accessing FICR, UICR, CACHEINFO, or CACHEDATA from non-secure state gives bus error”
  • Added: No. 53. “Current consumption in normal voltage mode is higher in System ON idle”
  • Added: No. 54. “Current consumption in normal voltage mode is higher in System ON idle and System OFF”
  • Added: No. 55. “Bits in RESETREAS are set when they should not be”
  • Added: No. 57. “EVENTS_FRAMESTART and PUBLISH_FRAMESTART registers are not functional”
  • Added: No. 58. “BYPASS in CONFIG.CLKCONFIG is not functional”
  • Added: No. 59. “QDEC is not functional”
  • Added: No. 65. “Events are not generated when switching from scan mode to no-scan mode with BURST disabled”
  • Added: No. 69. “VREGMAIN configuration is not retained in System OFF”
  • Added: No. 72. “Current consumption in high voltage mode is higher in System ON idle and System OFF”
Parent topic: nRF5340 Engineering A Errata