[220] CPU: RAM is not ready when written

This anomaly applies to Revision 2, build codes CIAA-EA0, CIAA-Ex0, QFAA-Ex0.

It was inherited from the previous IC revision Revision 1.

Symptoms

Memory is not written in the first cycle after wake-up.

Conditions

The following consecutive events occur:
  1. Either 1 MHz or 32 MHz peripheral clock state changes.
  2. After one to four 16 MHz cycles the DMA channel stops while the CPU is in sleep.
  3. An event or interrupt comes three 64 MHz cycles after the DMA channel stops.

Consequences

The address of the next instruction is not written to the stack. In stack frame, the link register is corrupted.

Workaround

Disable IRQ while using WFE by inserting the following code:

SCB->SCR |= SCB_SCR_SEVONPEND_Msk;
__disable_irq();
__WFE();
__nop();__nop();__nop();__nop();
__enable_irq();
This workaround is included in SoftDevice 1xx version 8.0 and later. SoftDevice v7.0.1 includes an alternative workaround which does not support FPU being enabled.