Macros | |
#define | NRFX_SPIS_ENABLED |
Set to 1 to activate. More... | |
#define | NRFX_SPIS0_ENABLED |
Enable SPIS0 instance. More... | |
#define | NRFX_SPIS1_ENABLED |
Enable SPIS1 instance. More... | |
#define | NRFX_SPIS2_ENABLED |
Enable SPIS2 instance. More... | |
#define | NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY |
Interrupt priority. More... | |
#define | NRFX_SPIS_DEFAULT_DEF |
SPIS default DEF character. More... | |
#define | NRFX_SPIS_DEFAULT_ORC |
SPIS default ORC character. More... | |
#define | NRFX_SPIS_CONFIG_LOG_ENABLED |
Enables logging in the module. More... | |
#define | NRFX_SPIS_CONFIG_LOG_LEVEL |
Default Severity level. More... | |
#define | NRFX_SPIS_CONFIG_INFO_COLOR |
ANSI escape code prefix. More... | |
#define | NRFX_SPIS_CONFIG_DEBUG_COLOR |
ANSI escape code prefix. More... | |
#define | NRFX_SPIS_NRF52_ANOMALY_109_WORKAROUND_ENABLED |
Enables nRF52 Anomaly 109 workaround for SPIS. More... | |
#define NRFX_SPIS0_ENABLED |
Enable SPIS0 instance.
Set to 1 to activate.
#define NRFX_SPIS1_ENABLED |
Enable SPIS1 instance.
Set to 1 to activate.
#define NRFX_SPIS2_ENABLED |
Enable SPIS2 instance.
Set to 1 to activate.
#define NRFX_SPIS_CONFIG_DEBUG_COLOR |
ANSI escape code prefix.
Following options are available:
#define NRFX_SPIS_CONFIG_INFO_COLOR |
ANSI escape code prefix.
Following options are available:
#define NRFX_SPIS_CONFIG_LOG_ENABLED |
Enables logging in the module.
Set to 1 to activate.
#define NRFX_SPIS_CONFIG_LOG_LEVEL |
Default Severity level.
Following options are available:
#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY |
Interrupt priority.
Following options are available:
#define NRFX_SPIS_DEFAULT_DEF |
SPIS default DEF character.
Minimum value: 0 Maximum value: 255
#define NRFX_SPIS_DEFAULT_ORC |
SPIS default ORC character.
Minimum value: 0 Maximum value: 255
#define NRFX_SPIS_ENABLED |
Set to 1 to activate.
#define NRFX_SPIS_NRF52_ANOMALY_109_WORKAROUND_ENABLED |
Enables nRF52 Anomaly 109 workaround for SPIS.
The workaround uses a GPIOTE channel to generate interrupts on falling edges detected on the CSN line. This will make the CPU active for the moment when SPIS starts DMA transfers, and this way the transfers will be protected. This workaround uses GPIOTE driver, so this driver must be enabled as well.
Set to 1 to activate.