Macros | |
#define | SPIS_ENABLED |
Set to 1 to activate. More... | |
#define | SPIS_DEFAULT_CONFIG_IRQ_PRIORITY |
Interrupt priority. More... | |
#define | SPIS_DEFAULT_MODE |
Mode. More... | |
#define | SPIS_DEFAULT_BIT_ORDER |
SPIS default bit order. More... | |
#define | SPIS_DEFAULT_DEF |
SPIS default DEF character. More... | |
#define | SPIS_DEFAULT_ORC |
SPIS default ORC character. More... | |
#define | SPIS0_ENABLED |
Enable SPIS0 instance. More... | |
#define | SPIS1_ENABLED |
Enable SPIS1 instance. More... | |
#define | SPIS2_ENABLED |
Enable SPIS2 instance. More... | |
#define | SPIS_NRF52_ANOMALY_109_WORKAROUND_ENABLED |
Enables nRF52 Anomaly 109 workaround for SPIS. More... | |
#define SPIS0_ENABLED |
Enable SPIS0 instance.
Set to 1 to activate.
#define SPIS1_ENABLED |
Enable SPIS1 instance.
Set to 1 to activate.
#define SPIS2_ENABLED |
Enable SPIS2 instance.
Set to 1 to activate.
#define SPIS_DEFAULT_BIT_ORDER |
SPIS default bit order.
Following options are available:
#define SPIS_DEFAULT_CONFIG_IRQ_PRIORITY |
Interrupt priority.
Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
Following options are available:
#define SPIS_DEFAULT_DEF |
SPIS default DEF character.
Minimum value: 0 Maximum value: 255
#define SPIS_DEFAULT_MODE |
Mode.
Following options are available:
#define SPIS_DEFAULT_ORC |
SPIS default ORC character.
Minimum value: 0 Maximum value: 255
#define SPIS_ENABLED |
Set to 1 to activate.
#define SPIS_NRF52_ANOMALY_109_WORKAROUND_ENABLED |
Enables nRF52 Anomaly 109 workaround for SPIS.
The workaround uses a GPIOTE channel to generate interrupts on falling edges detected on the CSN line. This will make the CPU active for the moment when SPIS starts DMA transfers, and this way the transfers will be protected. This workaround uses GPIOTE driver, so this driver must be enabled as well.
Set to 1 to activate.