TWI master with EasyDMA (TWIM) is a two-wire half-duplex master which can communicate with multiple slave devices connected to the same bus
The two-wire interface can communicate with a bi-directional wired-AND bus with two lines (SCL, SDA). The protocol makes it possible to interconnect up to 127 individually addressable devices. TWIM is not compatible with CBUS.
The GPIOs used for each two-wire interface line can be chosen from any GPIO on the device and are independently configurable. This enables great flexibility in device pinout and efficient use of board space and signal routing.
A typical TWI setup consists of one master and one or more slaves. For an example, see Figure 2. This TWIM is only able to operate as a single master on the TWI bus. Multi-master bus configuration is not supported.
This TWI master supports clock stretching performed by the slaves. The TWI master is started by triggering the STARTTX or STARTRX tasks, and stopped by triggering the STOP task. The TWI master will generate a STOPPED event when it has stopped following a STOP task.
The TWI master cannot get stopped while it is suspended, so the STOP task has to be issued after the TWI master has been resumed.
After the TWI master is started, the STARTTX task or the STARTRX task should not be triggered again before the TWI master has stopped, i.e. following a LASTRX, LASTTX or STOPPED event.
If a NACK is clocked in from the slave, the TWI master will generate an ERROR event.
The TWI master shares registers and other resources with other peripherals that have the same ID as the TWI master. Therefore, you must disable all peripherals that have the same ID as the TWI master before the TWI master can be configured and used.
Disabling a peripheral that has the same ID as the TWI master will not reset any of the registers that are shared with the TWI master. It is therefore important to configure all relevant registers explicitly to secure that the TWI master operates correctly.
The Instantiation table in Instantiation shows which peripherals have the same ID as the TWI.
The TWI master implements EasyDMA for reading and writing to and from the RAM.
If the TXD.PTR and the RXD.PTR are not pointing to the Data RAM region, an EasyDMA transfer may result in a HardFault or RAM corruption. See Memory for more information about the different memory regions.
The .PTR and .MAXCNT registers are double-buffered. They can be updated and prepared for the next RX/TX transmission immediately after having received the RXSTARTED/TXSTARTED event.
The STOPPED event indicates that EasyDMA has finished accessing the buffer in RAM.
EasyDMA supports one list type.
The supported list type is:
The EasyDMA array list can be represented by the data structure ArrayList_type.
For illustration, see the code example below. This data structure includes only a buffer with size equal to Channel.MAXCNT. EasyDMA will use the Channel.MAXCNT register to determine when the buffer is full. Replace 'Channel' by the specific data channel you want to use, for instance 'NRF_SPIM->RXD', 'NRF_SPIM->TXD', 'NRF_TWIM->RXD', etc.
The Channel.MAXCNT register cannot be specified larger than the actual size of the buffer. If Channel.MAXCNT is specified larger than the size of the buffer, the EasyDMA channel may overflow the buffer.
This array list does not provide a mechanism to explicitly specify where the next item in the list is located. Instead, it assumes that the list is organized as a linear array where items are located one after the other in RAM.
#define BUFFER_SIZE 4 typedef struct ArrayList { uint8_t buffer[BUFFER_SIZE]; } ArrayList_type; ArrayList_type MyArrayList[3]; //replace 'Channel' below by the specific data channel you want to use, // for instance 'NRF_SPIM->RXD', 'NRF_TWIM->RXD', etc. Channel.MAXCNT = BUFFER_SIZE; Channel.PTR = &MyArrayList;
A TWI master write sequence is started by triggering the STARTTX task. After the STARTTX task has been triggered, the TWI master will generate a start condition on the TWI bus, followed by clocking out the address and the READ/WRITE bit set to 0 (WRITE=0, READ=1).
The address must match the address of the slave device that the master wants to write to. The READ/WRITE bit is followed by an ACK/NACK bit (ACK=0 or NACK=1) generated by the slave.
After receiving the ACK bit, the TWI master will clock out the data bytes found in the transmit buffer located in RAM at the address specified in the TXD.PTR register. Each byte clocked out from the master will be followed by an ACK/NACK bit clocked in from the slave.
A typical TWI master write sequence is illustrated in Figure 4. Occurrence 2 in the figure illustrates clock stretching performed by the TWI master following a SUSPEND task.
A SUSPENDED event indicates that the SUSPEND task has taken effect; this event can be used to synchronize the software.
The TWI master will generate a LASTTX event when it starts to transmit the last byte, this is illustrated in Figure 4
The TWI master is stopped by triggering the STOP task, this task should be triggered during the transmission of the last byte to secure that the TWI will stop as fast as possible after sending the last byte. It is safe to use the shortcut between LASTTX and STOP to accomplish this.
Note that the TWI master does not stop by itself when the whole RAM buffer has been sent, or when an error occurs. The STOP task must be issued, through the use of a local or PPI shortcut, or in software as part of the error handler.
The TWI master cannot get stopped while it is suspended, so the STOP task has to be issued after the TWI master has been resumed.
A TWI master read sequence is started by triggering the STARTRX task. After the STARTRX task has been triggered the TWI master will generate a start condition on the TWI bus, followed by clocking out the address and the READ/WRITE bit set to 1 (WRITE = 0, READ = 1). The address must match the address of the slave device that the master wants to read from. The READ/WRITE bit is followed by an ACK/NACK bit (ACK=0 or NACK = 1) generated by the slave.
After having sent the ACK bit the TWI slave will send data to the master using the clock generated by the master.
Data received will be stored in RAM at the address specified in the RXD.PTR register. The TWI master will generate an ACK after all but the last byte received from the slave. The TWI master will generate a NACK after the last byte received to indicate that the read sequence shall stop.
A typical TWI master read sequence is illustrated in Figure 5. Occurrence 2 in the figure illustrates clock stretching performed by the TWI master following a SUSPEND task.
A SUSPENDED event indicates that the SUSPEND task has taken effect; this event can be used to synchronize the software.
The TWI master will generate a LASTRX event when it is ready to receive the last byte, this is illustrated in Figure 5. If RXD.MAXCNT > 1 the LASTRX event is generated after sending the ACK of the previously received byte. If RXD.MAXCNT = 1 the LASTRX event is generated after receiving the ACK following the address and READ bit.
The TWI master is stopped by triggering the STOP task, this task must be triggered before the NACK bit is supposed to be transmitted. The STOP task can be triggered at any time during the reception of the last byte. It is safe to use the shortcut between LASTRX and STOP to accomplish this.
Note that the TWI master does not stop by itself when the RAM buffer is full, or when an error occurs. The STOP task must be issued, through the use of a local or PPI shortcut, or in software as part of the error handler.
The TWI master cannot get stopped while it is suspended, so the STOP task has to be issued after the TWI master has been resumed.
A typical repeated start sequence is one in which the TWI master writes two bytes to the slave followed by reading four bytes from the slave. This example uses shortcuts to perform the simplest type of repeated start sequence, i.e. one write followed by one read. The same approach can be used to perform a repeated start sequence where the sequence is read followed by write.
The figure Figure 6 illustrates this:
If a more complex repeated start sequence is needed and the TWI firmware drive is serviced in a low priority interrupt it may be necessary to use the SUSPEND task and SUSPENDED event to guarantee that the correct tasks are generated at the correct time. This is illustrated in Figure 7.
When putting the system in low power and the peripheral is not needed, lowest possible power consumption is achieved by stopping, and then disabling the peripheral.
The STOP task may not be always needed (the peripheral might already be stopped), but if it is sent, software shall wait until the STOPPED event was received as a response before disabling the peripheral through the ENABLE register.
The SCL and SDA signals associated with the TWI master are mapped to physical pins according to the configuration specified in the PSEL.SCL and PSEL.SDA registers respectively.
The PSEL.SCL and PSEL.SDA registers and their configurations are only used as long as the TWI master is enabled, and retained only as long as the device is in ON mode. When the peripheral is disabled, the pins will behave as regular GPIOs, and use the configuration in their respective OUT bit field and PIN_CNF[n] register. PSEL.SCL, PSEL.SDA must only be configured when the TWI master is disabled.
To secure correct signal levels on the pins used by the TWI master when the system is in OFF mode, and when the TWI master is disabled, these pins must be configured in the GPIO peripheral as described in Table 1.
Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in unpredictable behavior.
TWI master signal | TWI master pin | Direction | Output value | Drive strength |
---|---|---|---|---|
SCL | As specified in PSEL.SCL | Input | Not applicable | S0D1 |
SDA | As specified in PSEL.SDA | Input | Not applicable | S0D1 |
Base address | Peripheral | Instance | Description | Configuration | |
---|---|---|---|---|---|
0x40003000 | TWIM | TWIM0 |
Two-wire interface master 0 |
||
0x40004000 | TWIM | TWIM1 |
Two-wire interface master 1 |
Register | Offset | Description | |
---|---|---|---|
TASKS_STARTRX | 0x000 |
Start TWI receive sequence |
|
TASKS_STARTTX | 0x008 |
Start TWI transmit sequence |
|
TASKS_STOP | 0x014 |
Stop TWI transaction. Must be issued while the TWI master is not suspended. |
|
TASKS_SUSPEND | 0x01C |
Suspend TWI transaction |
|
TASKS_RESUME | 0x020 |
Resume TWI transaction |
|
EVENTS_STOPPED | 0x104 |
TWI stopped |
|
EVENTS_ERROR | 0x124 |
TWI error |
|
EVENTS_SUSPENDED | 0x148 |
Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. |
|
EVENTS_RXSTARTED | 0x14C |
Receive sequence started |
|
EVENTS_TXSTARTED | 0x150 |
Transmit sequence started |
|
EVENTS_LASTRX | 0x15C |
Byte boundary, starting to receive the last byte |
|
EVENTS_LASTTX | 0x160 |
Byte boundary, starting to transmit the last byte |
|
SHORTS | 0x200 |
Shortcut register |
|
INTEN | 0x300 |
Enable or disable interrupt |
|
INTENSET | 0x304 |
Enable interrupt |
|
INTENCLR | 0x308 |
Disable interrupt |
|
ERRORSRC | 0x4C4 |
Error source |
|
ENABLE | 0x500 |
Enable TWIM |
|
PSEL.SCL | 0x508 |
Pin select for SCL signal |
|
PSEL.SDA | 0x50C |
Pin select for SDA signal |
|
FREQUENCY | 0x524 |
TWI frequency |
|
RXD.PTR | 0x534 |
Data pointer |
|
RXD.MAXCNT | 0x538 |
Maximum number of bytes in receive buffer |
|
RXD.AMOUNT | 0x53C |
Number of bytes transferred in the last transaction |
|
RXD.LIST | 0x540 |
EasyDMA list type |
|
TXD.PTR | 0x544 |
Data pointer |
|
TXD.MAXCNT | 0x548 |
Maximum number of bytes in transmit buffer |
|
TXD.AMOUNT | 0x54C |
Number of bytes transferred in the last transaction |
|
TXD.LIST | 0x550 |
EasyDMA list type |
|
ADDRESS | 0x588 |
Address used in the TWI transfer |
Address offset: 0x200
Shortcut register
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Id | F | D | C | B | A | ||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
LASTTX_STARTRX |
Shortcut between LASTTX event and STARTRX task See EVENTS_LASTTX and TASKS_STARTRX |
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Disabled |
0 |
Disable shortcut |
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Enabled |
1 |
Enable shortcut |
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B | RW |
LASTTX_SUSPEND |
Shortcut between LASTTX event and SUSPEND task See EVENTS_LASTTX and TASKS_SUSPEND |
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Disabled |
0 |
Disable shortcut |
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Enabled |
1 |
Enable shortcut |
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C | RW |
LASTTX_STOP |
Shortcut between LASTTX event and STOP task See EVENTS_LASTTX and TASKS_STOP |
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Disabled |
0 |
Disable shortcut |
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Enabled |
1 |
Enable shortcut |
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D | RW |
LASTRX_STARTTX |
Shortcut between LASTRX event and STARTTX task See EVENTS_LASTRX and TASKS_STARTTX |
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Disabled |
0 |
Disable shortcut |
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Enabled |
1 |
Enable shortcut |
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F | RW |
LASTRX_STOP |
Shortcut between LASTRX event and STOP task See EVENTS_LASTRX and TASKS_STOP |
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Disabled |
0 |
Disable shortcut |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Enable shortcut |
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Address offset: 0x300
Enable or disable interrupt
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Id | J | I | H | G | F | D | A | ||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
STOPPED |
Enable or disable interrupt for STOPPED event See EVENTS_STOPPED |
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Disabled |
0 |
Disable |
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Enabled |
1 |
Enable |
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D | RW |
ERROR |
Enable or disable interrupt for ERROR event See EVENTS_ERROR |
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Disabled |
0 |
Disable |
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Enabled |
1 |
Enable |
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F | RW |
SUSPENDED |
Enable or disable interrupt for SUSPENDED event See EVENTS_SUSPENDED |
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Disabled |
0 |
Disable |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Enable |
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G | RW |
RXSTARTED |
Enable or disable interrupt for RXSTARTED event See EVENTS_RXSTARTED |
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Disabled |
0 |
Disable |
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Enabled |
1 |
Enable |
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H | RW |
TXSTARTED |
Enable or disable interrupt for TXSTARTED event See EVENTS_TXSTARTED |
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Disabled |
0 |
Disable |
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Enabled |
1 |
Enable |
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I | RW |
LASTRX |
Enable or disable interrupt for LASTRX event See EVENTS_LASTRX |
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Disabled |
0 |
Disable |
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Enabled |
1 |
Enable |
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J | RW |
LASTTX |
Enable or disable interrupt for LASTTX event See EVENTS_LASTTX |
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Disabled |
0 |
Disable |
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Enabled |
1 |
Enable |
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Address offset: 0x304
Enable interrupt
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Id | J | I | H | G | F | D | A | ||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
STOPPED |
Write '1' to Enable interrupt for STOPPED event See EVENTS_STOPPED |
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Set |
1 |
Enable |
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Disabled |
0 |
Read: Disabled |
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Enabled |
1 |
Read: Enabled |
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D | RW |
ERROR |
Write '1' to Enable interrupt for ERROR event See EVENTS_ERROR |
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Set |
1 |
Enable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
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Enabled |
1 |
Read: Enabled |
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F | RW |
SUSPENDED |
Write '1' to Enable interrupt for SUSPENDED event See EVENTS_SUSPENDED |
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Set |
1 |
Enable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
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Enabled |
1 |
Read: Enabled |
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G | RW |
RXSTARTED |
Write '1' to Enable interrupt for RXSTARTED event See EVENTS_RXSTARTED |
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Set |
1 |
Enable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
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Enabled |
1 |
Read: Enabled |
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H | RW |
TXSTARTED |
Write '1' to Enable interrupt for TXSTARTED event See EVENTS_TXSTARTED |
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Set |
1 |
Enable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
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I | RW |
LASTRX |
Write '1' to Enable interrupt for LASTRX event See EVENTS_LASTRX |
||||||||||||||||||||||||||||||||
Set |
1 |
Enable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
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Enabled |
1 |
Read: Enabled |
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J | RW |
LASTTX |
Write '1' to Enable interrupt for LASTTX event See EVENTS_LASTTX |
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Set |
1 |
Enable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
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Enabled |
1 |
Read: Enabled |
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Address offset: 0x308
Disable interrupt
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Id | J | I | H | G | F | D | A | ||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
STOPPED |
Write '1' to Disable interrupt for STOPPED event See EVENTS_STOPPED |
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Clear |
1 |
Disable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
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D | RW |
ERROR |
Write '1' to Disable interrupt for ERROR event See EVENTS_ERROR |
||||||||||||||||||||||||||||||||
Clear |
1 |
Disable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
F | RW |
SUSPENDED |
Write '1' to Disable interrupt for SUSPENDED event See EVENTS_SUSPENDED |
||||||||||||||||||||||||||||||||
Clear |
1 |
Disable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
G | RW |
RXSTARTED |
Write '1' to Disable interrupt for RXSTARTED event See EVENTS_RXSTARTED |
||||||||||||||||||||||||||||||||
Clear |
1 |
Disable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
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H | RW |
TXSTARTED |
Write '1' to Disable interrupt for TXSTARTED event See EVENTS_TXSTARTED |
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Clear |
1 |
Disable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
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I | RW |
LASTRX |
Write '1' to Disable interrupt for LASTRX event See EVENTS_LASTRX |
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Clear |
1 |
Disable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
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J | RW |
LASTTX |
Write '1' to Disable interrupt for LASTTX event See EVENTS_LASTTX |
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Clear |
1 |
Disable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
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Enabled |
1 |
Read: Enabled |
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Address offset: 0x4C4
Error source
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Id | C | B | A | ||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
OVERRUN |
Overrun error A new byte was received before previous byte got transferred into RXD buffer. (Previous data is lost) |
||||||||||||||||||||||||||||||||
NotReceived |
0 |
Error did not occur |
|||||||||||||||||||||||||||||||||
Received |
1 |
Error occurred |
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B | RW |
ANACK |
NACK received after sending the address (write '1' to clear) |
||||||||||||||||||||||||||||||||
NotReceived |
0 |
Error did not occur |
|||||||||||||||||||||||||||||||||
Received |
1 |
Error occurred |
|||||||||||||||||||||||||||||||||
C | RW |
DNACK |
NACK received after sending a data byte (write '1' to clear) |
||||||||||||||||||||||||||||||||
NotReceived |
0 |
Error did not occur |
|||||||||||||||||||||||||||||||||
Received |
1 |
Error occurred |
|||||||||||||||||||||||||||||||||
Address offset: 0x500
Enable TWIM
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Id | A | A | A | A | |||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
ENABLE |
Enable or disable TWIM |
||||||||||||||||||||||||||||||||
Disabled |
0 |
Disable TWIM |
|||||||||||||||||||||||||||||||||
Enabled |
6 |
Enable TWIM |
|||||||||||||||||||||||||||||||||
Address offset: 0x508
Pin select for SCL signal
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Id | B | A | A | A | A | A | |||||||||||||||||||||||||||||
Reset 0xFFFFFFFF | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
PIN |
[0..31] |
Pin number |
|||||||||||||||||||||||||||||||
B | RW |
CONNECT |
Connection |
||||||||||||||||||||||||||||||||
Disconnected |
1 |
Disconnect |
|||||||||||||||||||||||||||||||||
Connected |
0 |
Connect |
|||||||||||||||||||||||||||||||||
Address offset: 0x50C
Pin select for SDA signal
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Id | B | A | A | A | A | A | |||||||||||||||||||||||||||||
Reset 0xFFFFFFFF | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
PIN |
[0..31] |
Pin number |
|||||||||||||||||||||||||||||||
B | RW |
CONNECT |
Connection |
||||||||||||||||||||||||||||||||
Disconnected |
1 |
Disconnect |
|||||||||||||||||||||||||||||||||
Connected |
0 |
Connect |
|||||||||||||||||||||||||||||||||
Address offset: 0x524
TWI frequency
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Id | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | |||
Reset 0x04000000 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
FREQUENCY |
TWI master clock frequency |
||||||||||||||||||||||||||||||||
K100 |
0x01980000 |
100 kbps |
|||||||||||||||||||||||||||||||||
K250 |
0x04000000 |
250 kbps |
|||||||||||||||||||||||||||||||||
K400 |
0x06400000 |
400 kbps |
|||||||||||||||||||||||||||||||||
Address offset: 0x534
Data pointer
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Id | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | |||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
PTR |
Data pointer |
||||||||||||||||||||||||||||||||
Address offset: 0x538
Maximum number of bytes in receive buffer
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Id | A | A | A | A | A | A | A | A | |||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
MAXCNT |
[1..255] |
Maximum number of bytes in receive buffer |
|||||||||||||||||||||||||||||||
Address offset: 0x53C
Number of bytes transferred in the last transaction
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Id | A | A | A | A | A | A | A | A | |||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | R |
AMOUNT |
Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. |
||||||||||||||||||||||||||||||||
Address offset: 0x540
EasyDMA list type
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Id | A | A | A | ||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
LIST |
List type |
||||||||||||||||||||||||||||||||
Disabled |
0 |
Disable EasyDMA list |
|||||||||||||||||||||||||||||||||
ArrayList |
1 |
Use array list |
|||||||||||||||||||||||||||||||||
Address offset: 0x544
Data pointer
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Id | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | |||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
PTR |
Data pointer |
||||||||||||||||||||||||||||||||
Address offset: 0x548
Maximum number of bytes in transmit buffer
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Id | A | A | A | A | A | A | A | A | |||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
MAXCNT |
[1..255] |
Maximum number of bytes in transmit buffer |
|||||||||||||||||||||||||||||||
Address offset: 0x54C
Number of bytes transferred in the last transaction
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Id | A | A | A | A | A | A | A | A | |||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | R |
AMOUNT |
Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. |
||||||||||||||||||||||||||||||||
Address offset: 0x550
EasyDMA list type
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Id | A | A | A | ||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
LIST |
List type |
||||||||||||||||||||||||||||||||
Disabled |
0 |
Disable EasyDMA list |
|||||||||||||||||||||||||||||||||
ArrayList |
1 |
Use array list |
|||||||||||||||||||||||||||||||||
Address offset: 0x588
Address used in the TWI transfer
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Id | A | A | A | A | A | A | A | ||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
ADDRESS |
Address used in the TWI transfer |
||||||||||||||||||||||||||||||||
Symbol | Description | Min. | Typ. | Max. | Units | ||||
---|---|---|---|---|---|---|---|---|---|
fTWIM |
Bit rates for TWIM1 |
100 | 400 | kbps | |||||
ITWIM,100kbps |
Run current for TWIM, 100 kbps |
50 | µA | ||||||
ITWIM,400kbps |
Run current for TWIM, 400 kbps |
50 | µA | ||||||
tTWIM,START,LP |
Time from STARTRX/STARTTX task to transmission started, Low power mode |
tTWIM,START,CL + tSTART_HFINT | µs | ||||||
tTWIM,START,CL |
Time from STARTRX/STARTTX task to transmission started, Constant latency mode |
1.5 | µs |
Symbol | Description | Min. | Typ. | Max. | Units | ||||
---|---|---|---|---|---|---|---|---|---|
fTWIM,SCL,100kbps |
SCL clock frequency, 100 kbps |
100 | kHz | ||||||
fTWIM,SCL,250kbps |
SCL clock frequency, 250 kbps |
250 | kHz | ||||||
fTWIM,SCL,400kbps |
SCL clock frequency, 400 kbps |
400 | kHz | ||||||
tTWIM,SU_DAT |
Data setup time before positive edge on SCL – all modes |
300 | ns | ||||||
tTWIM,HD_DAT |
Data hold time after negative edge on SCL – all modes |
500 | ns | ||||||
tTWIM,HD_STA,100kbps |
TWIM master hold time for START and repeated START condition, 100 kbps |
10000 | ns | ||||||
tTWIM,HD_STA,250kbps |
TWIM master hold time for START and repeated START condition, 250kbps |
4000 | ns | ||||||
tTWIM,HD_STA,400kbps |
TWIM master hold time for START and repeated START condition, 400 kbps |
2500 | ns | ||||||
tTWIM,SU_STO,100kbps |
TWIM master setup time from SCL high to STOP condition, 100 kbps |
5000 | ns | ||||||
tTWIM,SU_STO,250kbps |
TWIM master setup time from SCL high to STOP condition, 250 kbps |
2000 | ns | ||||||
tTWIM,SU_STO,400kbps |
TWIM master setup time from SCL high to STOP condition, 400 kbps |
1250 | ns | ||||||
tTWIM,BUF,100kbps |
TWIM master bus free time between STOP and START conditions, 100 kbps |
5800 | ns | ||||||
tTWIM,BUF,250kbps |
TWIM master bus free time between STOP and START conditions, 250 kbps |
2700 | ns | ||||||
tTWIM,BUF,400kbps |
TWIM master bus free time between STOP and START conditions, 400 kbps |
2100 | ns |