The Quadrature decoder (QDEC) provides buffered decoding of quadrature-encoded sensor signals. It is suitable for mechanical and optical sensors.
The sample period and accumulation are configurable to match application requirements. The QDEC provides the following:
The QDEC decodes the output from an incremental motion encoder by sampling the QDEC phase input pins (A and B).
The off-chip quadrature encoder is an incremental motion encoder outputting two waveforms, phase A and phase B. The two output waveforms are always 90 degrees out of phase, meaning that one always changes level before the other. The direction of movement is indicated by which of these two waveforms that changes level first. Invalid transitions may occur, that is when the two waveforms switch simultaneously. This may occur if the wheel rotates too fast relative to the sample rate set for the decoder.
The QDEC decodes the output from the off-chip encoder by sampling the QDEC phase input pins (A and B) at a fixed rate as specified in the SAMPLEPER register.
If the SAMPLEPER value needs to be changed, the QDEC shall be stopped using the STOP task. SAMPLEPER can be then changed upon receiving the STOPPED event, and QDEC can be restarted using the START task. Failing to do so may result in unpredictable behaviour.
It is good practice to change other registers (LEDPOL, REPORTPER, DBFEN and LEDPRE) only when the QDEC is stopped.
When started, the decoder continuously samples the two input waveforms and decodes these by comparing the current sample pair (n) with the previous sample pair (n-1).
The decoding of the sample pairs is described in the table below.
Previous sample pair(n - 1) | Current samples pair(n) | SAMPLE register | ACC operation | ACCDBL operation | Description | ||
---|---|---|---|---|---|---|---|
A | B | A | B | ||||
0 | 0 | 0 | 0 | 0 | No change | No change | No movement |
0 | 0 | 0 | 1 | 1 | Increment | No change | Movement in positive direction |
0 | 0 | 1 | 0 | -1 | Decrement | No change | Movement in negative direction |
0 | 0 | 1 | 1 | 2 | No change | Increment | Error: Double transition |
0 | 1 | 0 | 0 | -1 | Decrement | No change | Movement in negative direction |
0 | 1 | 0 | 1 | 0 | No change | No change | No movement |
0 | 1 | 1 | 0 | 2 | No change | Increment | Error: Double transition |
0 | 1 | 1 | 1 | 1 | Increment | No change | Movement in positive direction |
1 | 0 | 0 | 0 | 1 | Increment | No change | Movement in positive direction |
1 | 0 | 0 | 1 | 2 | No change | Increment | Error: Double transition |
1 | 0 | 1 | 0 | 0 | No change | No change | No movement |
1 | 0 | 1 | 1 | -1 | Decrement | No change | Movement in negative direction |
1 | 1 | 0 | 0 | 2 | No change | Increment | Error: Double transition |
1 | 1 | 0 | 1 | -1 | Decrement | No change | Movement in negative direction |
1 | 1 | 1 | 0 | 1 | Increment | No change | Movement in positive direction |
1 | 1 | 1 | 1 | 0 | No change | No change | No movement |
The LED output follows the sample period, and the LED is switched on a given period before sampling and switched off immediately after the inputs are sampled. The period the LED is switched on before sampling is given in the LEDPRE register.
The LED output pin polarity is specified in the LEDPOL register.
For using off-chip mechanical encoders not requiring a LED, the LED output can be disabled by writing value 'Disconnected' to the CONNECT field of the PSEL.LED register. In this case the QDEC will not acquire access to a LED output pin and the pin can be used for other purposes by the CPU.
Each of the two-phase inputs have digital debounce filters.
When enabled through the DBFEN register, the filter inputs are sampled at a fixed 1 MHz frequency during the entire sample period (which is specified in the SAMPLEPER register), and the filters require all of the samples within this sample period to equal before the input signal is accepted and transferred to the output of the filter.
As a result, only input signal with a steady state longer than twice the period specified in SAMPLEPER are guaranteed to pass through the filter, and any signal with a steady state shorter than SAMPLEPER will always be suppressed by the filter. (This is assumed that the frequency during the debounce period never exceeds 500 kHz (as required by the Nyquist theorem when using a 1 MHz sample frequency).
The LED will always be ON when the debounce filters are enabled, as the inputs in this case will be sampled continuously.
Note that when when the debounce filters are enabled, displacements reported by the QDEC peripheral are delayed by one SAMPLEPER period.
The quadrature decoder contains two accumulator registers, ACC and ACCDBL, that accumulate respectively valid motion sample values and the number of detected invalid samples (double transitions).
The ACC register will accumulate all valid values (1/-1) written to the SAMPLE register. This can be useful for preventing hard real-time requirements from being enforced on the application. When using the ACC register the application does not need to read every single sample from the SAMPLE register, but can instead fetch the ACC register whenever it fits the application. The ACC register will always hold the relative movement of the external mechanical device since the previous clearing of the ACC register. Sample values indicating a double transition (2) will not be accumulated in the ACC register.
An ACCOF event will be generated if the ACC receives a SAMPLE value that would cause the register to overflow or underflow. Any SAMPLE value that would cause an ACC overflow or underflow will be discarded, but any samples not causing the ACC to overflow or underflow will still be accepted.
The accumulator ACCDBL accumulates the number of detected double transitions since the previous clearing of the ACCDBL register.
The ACC and ACCDBL registers can be cleared by the READCLRACC and subsequently read using the ACCREAD and ACCDBLREAD registers.
The ACC register can be separately cleared by the RDCLRACC and subsequently read using the ACCREAD registers.
The ACCDBL register can be separately cleared by the RDCLRDBL and subsequently read using the ACCDBLREAD registers.
The REPORTPER register allows automating the capture of several samples before it can send out a REPORTRDY event in case a non-null displacement has been captured and accumulated, and a DBLRDY event in case one or more double-displacements have been captured and accumulated. The REPORTPER field in this register selects after how many samples the accumulators contents are evaluated to send (or not) REPORTRDY and DBLRDY events.
Using the RDCLRACC task (manually sent upon receiving the event, or using the DBLRDY_RDCLRACC shortcut), ACCREAD can then be read.
In case at least one double transition has been captured and accumulated, a DBLRDY event is sent. Using the RDCLRDBL task (manually sent upon receiving the event, or using the DBLRDY_RDCLRDBL shortcut), ACCDBLREAD can then be read.
The QDEC uses a three-pin interface to the off-chip quadrature encoder.
These pins will be acquired when the QDEC is enabled in the ENABLE register. The pins acquired by the QDEC cannot be written by the CPU, but they can still be read by the CPU.
The pin numbers to be used for the QDEC are selected using the PSEL.n registers.
The Phase A, Phase B, and LED signals are mapped to physical pins according to the configuration specified in the PSEL.A, PSEL.B, and PSEL.LED registers respectively.
If the CONNECT field value 'Disconnected' is specified in any of these registers, the associated signal will not be connected to any physical pin. The PSEL.A, PSEL.B, and PSEL.LED registers and their configurations are only used as long as the QDEC is enabled, and retained only as long as the device is in ON mode. When the peripheral is disabled, the pins will behave as regular GPIOs, and use the configuration in their respective OUT bit field and PIN_CNF[n] register.
To secure correct behavior in the QDEC, the pins used by the QDEC must be configured in the GPIO peripheral as described in Table 2 before enabling the QDEC. This configuration must be retained in the GPIO for the selected IOs as long as the QDEC is enabled.
Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in unpredictable behavior.
QDEC signal | QDEC pin | Direction | Output value | Comment |
---|---|---|---|---|
Phase A | As specified in PSEL.A | Input | Not applicable | |
Phase B | As specified in PSEL.B | Input | Not applicable | |
LED | As specified in PSEL.LED | Input | Not applicable |
Base address | Peripheral | Instance | Description | Configuration | |
---|---|---|---|---|---|
0x40012000 | QDEC | QDEC |
Quadrature decoder |
Register | Offset | Description | |
---|---|---|---|
TASKS_START | 0x000 |
Task starting the quadrature decoder |
|
TASKS_STOP | 0x004 |
Task stopping the quadrature decoder |
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TASKS_READCLRACC | 0x008 |
Read and clear ACC and ACCDBL |
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TASKS_RDCLRACC | 0x00C |
Read and clear ACC |
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TASKS_RDCLRDBL | 0x010 |
Read and clear ACCDBL |
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EVENTS_SAMPLERDY | 0x100 |
Event being generated for every new sample value written to the SAMPLE register |
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EVENTS_REPORTRDY | 0x104 |
Non-null report ready |
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EVENTS_ACCOF | 0x108 |
ACC or ACCDBL register overflow |
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EVENTS_DBLRDY | 0x10C |
Double displacement(s) detected |
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EVENTS_STOPPED | 0x110 |
QDEC has been stopped |
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SHORTS | 0x200 |
Shortcut register |
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INTENSET | 0x304 |
Enable interrupt |
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INTENCLR | 0x308 |
Disable interrupt |
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ENABLE | 0x500 |
Enable the quadrature decoder |
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LEDPOL | 0x504 |
LED output pin polarity |
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SAMPLEPER | 0x508 |
Sample period |
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SAMPLE | 0x50C |
Motion sample value |
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REPORTPER | 0x510 |
Number of samples to be taken before REPORTRDY and DBLRDY events can be generated |
|
ACC | 0x514 |
Register accumulating the valid transitions |
|
ACCREAD | 0x518 |
Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task |
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PSEL.LED | 0x51C |
Pin select for LED signal |
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PSEL.A | 0x520 |
Pin select for A signal |
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PSEL.B | 0x524 |
Pin select for B signal |
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DBFEN | 0x528 |
Enable input debounce filters |
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LEDPRE | 0x540 |
Time period the LED is switched ON prior to sampling |
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ACCDBL | 0x544 |
Register accumulating the number of detected double transitions |
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ACCDBLREAD | 0x548 |
Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task |
Address offset: 0x200
Shortcut register
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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Id | G | F | E | D | C | B | A | ||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
REPORTRDY_READCLRACC |
Shortcut between REPORTRDY event and READCLRACC task See EVENTS_REPORTRDY and TASKS_READCLRACC |
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Disabled |
0 |
Disable shortcut |
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Enabled |
1 |
Enable shortcut |
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B | RW |
SAMPLERDY_STOP |
Shortcut between SAMPLERDY event and STOP task See EVENTS_SAMPLERDY and TASKS_STOP |
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Disabled |
0 |
Disable shortcut |
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Enabled |
1 |
Enable shortcut |
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C | RW |
REPORTRDY_RDCLRACC |
Shortcut between REPORTRDY event and RDCLRACC task See EVENTS_REPORTRDY and TASKS_RDCLRACC |
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Disabled |
0 |
Disable shortcut |
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Enabled |
1 |
Enable shortcut |
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D | RW |
REPORTRDY_STOP |
Shortcut between REPORTRDY event and STOP task See EVENTS_REPORTRDY and TASKS_STOP |
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Disabled |
0 |
Disable shortcut |
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Enabled |
1 |
Enable shortcut |
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E | RW |
DBLRDY_RDCLRDBL |
Shortcut between DBLRDY event and RDCLRDBL task See EVENTS_DBLRDY and TASKS_RDCLRDBL |
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Disabled |
0 |
Disable shortcut |
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Enabled |
1 |
Enable shortcut |
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F | RW |
DBLRDY_STOP |
Shortcut between DBLRDY event and STOP task See EVENTS_DBLRDY and TASKS_STOP |
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Disabled |
0 |
Disable shortcut |
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Enabled |
1 |
Enable shortcut |
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G | RW |
SAMPLERDY_READCLRACC |
Shortcut between SAMPLERDY event and READCLRACC task See EVENTS_SAMPLERDY and TASKS_READCLRACC |
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Disabled |
0 |
Disable shortcut |
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Enabled |
1 |
Enable shortcut |
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Address offset: 0x304
Enable interrupt
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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Id | E | D | C | B | A | ||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
SAMPLERDY |
Write '1' to Enable interrupt for SAMPLERDY event See EVENTS_SAMPLERDY |
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Set |
1 |
Enable |
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Disabled |
0 |
Read: Disabled |
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Enabled |
1 |
Read: Enabled |
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B | RW |
REPORTRDY |
Write '1' to Enable interrupt for REPORTRDY event See EVENTS_REPORTRDY |
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Set |
1 |
Enable |
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Disabled |
0 |
Read: Disabled |
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Enabled |
1 |
Read: Enabled |
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C | RW |
ACCOF |
Write '1' to Enable interrupt for ACCOF event See EVENTS_ACCOF |
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Set |
1 |
Enable |
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Disabled |
0 |
Read: Disabled |
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Enabled |
1 |
Read: Enabled |
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D | RW |
DBLRDY |
Write '1' to Enable interrupt for DBLRDY event See EVENTS_DBLRDY |
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Set |
1 |
Enable |
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Disabled |
0 |
Read: Disabled |
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Enabled |
1 |
Read: Enabled |
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E | RW |
STOPPED |
Write '1' to Enable interrupt for STOPPED event See EVENTS_STOPPED |
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Set |
1 |
Enable |
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Disabled |
0 |
Read: Disabled |
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Enabled |
1 |
Read: Enabled |
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Address offset: 0x308
Disable interrupt
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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Id | E | D | C | B | A | ||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
SAMPLERDY |
Write '1' to Disable interrupt for SAMPLERDY event See EVENTS_SAMPLERDY |
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Clear |
1 |
Disable |
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Disabled |
0 |
Read: Disabled |
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Enabled |
1 |
Read: Enabled |
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B | RW |
REPORTRDY |
Write '1' to Disable interrupt for REPORTRDY event See EVENTS_REPORTRDY |
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Clear |
1 |
Disable |
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Disabled |
0 |
Read: Disabled |
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Enabled |
1 |
Read: Enabled |
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C | RW |
ACCOF |
Write '1' to Disable interrupt for ACCOF event See EVENTS_ACCOF |
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Clear |
1 |
Disable |
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Disabled |
0 |
Read: Disabled |
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Enabled |
1 |
Read: Enabled |
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D | RW |
DBLRDY |
Write '1' to Disable interrupt for DBLRDY event See EVENTS_DBLRDY |
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Clear |
1 |
Disable |
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Disabled |
0 |
Read: Disabled |
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Enabled |
1 |
Read: Enabled |
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E | RW |
STOPPED |
Write '1' to Disable interrupt for STOPPED event See EVENTS_STOPPED |
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Clear |
1 |
Disable |
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Disabled |
0 |
Read: Disabled |
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Enabled |
1 |
Read: Enabled |
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Address offset: 0x500
Enable the quadrature decoder
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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Id | A | ||||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
ENABLE |
Enable or disable the quadrature decoder When enabled the decoder pins will be active. When disabled the quadrature decoder pins are not active and can be used as GPIO . |
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Disabled |
0 |
Disable |
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Enabled |
1 |
Enable |
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Address offset: 0x504
LED output pin polarity
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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Id | A | ||||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
LEDPOL |
LED output pin polarity |
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ActiveLow |
0 |
Led active on output pin low |
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ActiveHigh |
1 |
Led active on output pin high |
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Address offset: 0x508
Sample period
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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Id | A | A | A | A | |||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
SAMPLEPER |
Sample period. The SAMPLE register will be updated for every new sample |
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128us |
0 |
128 us |
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256us |
1 |
256 us |
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512us |
2 |
512 us |
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1024us |
3 |
1024 us |
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2048us |
4 |
2048 us |
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4096us |
5 |
4096 us |
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8192us |
6 |
8192 us |
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16384us |
7 |
16384 us |
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32ms |
8 |
32768 us |
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65ms |
9 |
65536 us |
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131ms |
10 |
131072 us |
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Address offset: 0x50C
Motion sample value
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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Id | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | |||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | R |
SAMPLE |
[-1..2] |
Last motion sample The value is a 2's complement value, and the sign gives the direction of the motion. The value '2' indicates a double transition. |
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Address offset: 0x510
Number of samples to be taken before REPORTRDY and DBLRDY events can be generated
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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Id | A | A | A | A | |||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
REPORTPER |
Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated The report period in [us] is given as: RPUS = SP * RP Where RPUS is the report period in [us/report], SP is the sample period in [us/sample] specified in SAMPLEPER, and RP is the report period in [samples/report] specified in REPORTPER . |
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10Smpl |
0 |
10 samples / report |
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40Smpl |
1 |
40 samples / report |
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80Smpl |
2 |
80 samples / report |
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120Smpl |
3 |
120 samples / report |
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160Smpl |
4 |
160 samples / report |
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200Smpl |
5 |
200 samples / report |
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240Smpl |
6 |
240 samples / report |
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280Smpl |
7 |
280 samples / report |
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1Smpl |
8 |
1 sample / report |
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Address offset: 0x514
Register accumulating the valid transitions
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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Id | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | |||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | R |
ACC |
[-1024..1023] |
Register accumulating all valid samples (not double transition) read from the SAMPLE register Double transitions ( SAMPLE = 2 ) will not be accumulated in this register. The value is a 32 bit 2's complement value. If a sample that would cause this register to overflow or underflow is received, the sample will be ignored and an overflow event ( ACCOF ) will be generated. The ACC register is cleared by triggering the READCLRACC or the RDCLRACC task. |
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Address offset: 0x518
Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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Id | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | |||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | R |
ACCREAD |
[-1024..1023] |
Snapshot of the ACC register. The ACCREAD register is updated when the READCLRACC or RDCLRACC task is triggered |
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Address offset: 0x51C
Pin select for LED signal
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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Id | B | A | A | A | A | A | |||||||||||||||||||||||||||||
Reset 0xFFFFFFFF | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
PIN |
[0..31] |
Pin number |
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B | RW |
CONNECT |
Connection |
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Disconnected |
1 |
Disconnect |
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Connected |
0 |
Connect |
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Address offset: 0x520
Pin select for A signal
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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Id | B | A | A | A | A | A | |||||||||||||||||||||||||||||
Reset 0xFFFFFFFF | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
PIN |
[0..31] |
Pin number |
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B | RW |
CONNECT |
Connection |
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Disconnected |
1 |
Disconnect |
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Connected |
0 |
Connect |
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Address offset: 0x524
Pin select for B signal
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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Id | B | A | A | A | A | A | |||||||||||||||||||||||||||||
Reset 0xFFFFFFFF | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
PIN |
[0..31] |
Pin number |
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B | RW |
CONNECT |
Connection |
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Disconnected |
1 |
Disconnect |
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Connected |
0 |
Connect |
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Address offset: 0x528
Enable input debounce filters
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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Id | A | ||||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
DBFEN |
Enable input debounce filters |
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Disabled |
0 |
Debounce input filters disabled |
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Enabled |
1 |
Debounce input filters enabled |
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Address offset: 0x540
Time period the LED is switched ON prior to sampling
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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Id | A | A | A | A | A | A | A | A | A | ||||||||||||||||||||||||||
Reset 0x00000010 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
LEDPRE |
[1..511] |
Period in us the LED is switched on prior to sampling |
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Address offset: 0x544
Register accumulating the number of detected double transitions
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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Id | A | A | A | A | |||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | R |
ACCDBL |
[0..15] |
Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). When this register has reached its maximum value the accumulation of double / illegal transitions will stop. An overflow event ( ACCOF ) will be generated if any double or illegal transitions are detected after the maximum value was reached. This field is cleared by triggering the READCLRACC or RDCLRDBL task. |
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Address offset: 0x548
Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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Id | A | A | A | A | |||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | R |
ACCDBLREAD |
[0..15] |
Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. |
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Symbol | Description | Min. | Typ. | Max. | Units | ||||
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IQDEC |
Run current |
5 | µA | ||||||
tSAMPLE |
Time between sampling signals from quadrature decoder |
128 | 131072 | µs | |||||
tLED |
Time from LED is turned on to signals are sampled |
0 | 511 | µs |