The CPU and all of the EasyDMAs are AHB bus masters on the AHB multilayer, while the RAM and various other modules are AHB slaves.
See Block diagram for an overview of which peripherals implement EasyDMA.
The CPU has exclusive access to all AHB slaves except for the RAM that can also be accessed by the EasyDMA.
Access rights to each of the RAM AHB slaves are resolved using the priority of the different bus masters in the system
See AHB multilayer priorities for information about the priority of the different AHB bus masters in the system. It is possible for two or more bus masters to have the same priority in cases where it is guaranteed by design that the related masters will never be able to access the same slave at the same time.
Each master connected to the AHB multilayer is assigned a priority.
| Bus master name | Priority | Description |
|---|---|---|
| CPU | Highest priority | |
| SPIS1 | Applies to SPIM1, SPIS1, TWIM1, TWIS1 | |
| RADIO | ||
| CCM/ECB/AAR | ||
| SAADC | ||
| UARTE | ||
| SERIAL0 | Applies to SPIM0, SPIS0, TWIM0, TWIS0 | |
| SERIAL2 | Applies to SPIM2, SPIS2 | |
| NFCT | ||
| I2S | I2S | |
| PDM | PDM | |
| PWM | Lowest priority | Applies to PWM0, PWM1, PWM2 |