Hardware peripherals

SoftDevice access types are used to indicate the availability of hardware peripherals to the application. The availability varies per hardware peripheral and depends on whether the SoftDevice is enabled or disabled.

Table 1. Hardware access type definitions
Access type Definition
Restricted

Used by the SoftDevice and outside the application sandbox.

The application has limited access through the SoftDevice API.
Blocked

Used by the SoftDevice and outside the application sandbox.

The application has no access.
Open

Not used by the SoftDevice.

The application has full access.
Table 2. Peripheral protection and usage by SoftDevice
ID Base address Instance

Access

SoftDevice enabled

Access

SoftDevice disabled
0 0x40000000 CLOCK Restricted Open
0 0x40000000 POWER Restricted Open
0 0x40000000 MPU Restricted Open
1 0x40001000 RADIO Blocked4 Open
2 0x40002000 UART0 Open Open
3 0x40003000 SPI0 / TWI0 Open Open
4 0x40004000 SPI1 / SPIS1 / TWI1 Open Open
...
6 0x40006000 GPIOTE Open Open
7 0x40007000 ADC Open Open
8 0x40008000 TIMER0 Blocked4 Open
9 0x40009000 TIMER1 Open Open
10 0x4000A000 TIMER2 Open Open
11 0x4000B000 RTC0 Blocked Open
12 0x4000C000 TEMP Restricted Open
13 0x4000D000 RNG Restricted Open
14 0x4000E000 ECB Restricted Open
15 0x4000F000 CCM Blocked4 Open
15 0x4000F000 AAR Blocked4 Open
16 0x40010000 WDT Open Open
17 0x40011000 RTC1 Open Open
18 0x40012000 QDEC Open Open
19 0x40013000 LPCOMP Open Open
20 0x40014000 SWI0 Open Open
21 0x40015000 SWI1 / Radio Notification Restricted5 Open
22 0x40016000 SWI2 / SoftDevice Event Blocked Open
23 0x40017000 SWI3 Open Open
24 0x40018000 SWI4 Blocked Open
25 0x40019000 SWI5 Blocked Open
...
30 0x4001E000 NVMC Restricted Open
31 0x4001F000 PPI Open1 Open
NA 0x10000000 FICR Blocked Blocked
NA 0x10001000 UICR Restricted Open
NA 0x50000000 GPIO P0 Open Open
NA 0xE000E100 NVIC Restricted3 Open
Parent topic: System on Chip resource requirements
1 See section Programmable peripheral interconnect (PPI) for limitations on the use of PPI when the SoftDevice is enabled.
2 See section Memory isolation and runtime protection and Peripheral runtime protection for limitations on the use of MWU when the SoftDevice is enabled.
3 Not protected. For robust system function, the application program must comply with the restriction and use the NVIC API for configuration when the SoftDevice is enabled.
4 Available to the application through the Radio Timeslot API, see Concurrent multiprotocol implementation using the Radio Timeslot API.
5 Blocked only when Radio Notification signal is enabled. See Application signals – software interrupts (SWI) for software interrupt allocation.
Documentation feedback | Developer Zone | Updated 2016-04-08