The Universal asynchronous receiver/transmitter with EasyDMA (UARTE) offers fast, full-duplex, asynchronous serial communication with built-in flow control (CTS, RTS) support in hardware at a rate up to 1 Mbps, and EasyDMA data transfer from/to RAM.
Listed here are the main features for UARTE:
The GPIOs used for each UART interface can be chosen from any GPIO on the device and are independently configurable. This enables great flexibility in device pinout and efficient use of board space and signal routing.
The UARTE shares registers and other resources with other peripherals that have the same ID as the UARTE.
Therefore, you must disable all peripherals that have the same ID as the UARTE before the UARTE can be configured and used. Disabling a peripheral that has the same ID as the UARTE will not reset any of the registers that are shared with the UARTE. It is therefore important to configure all relevant UARTE registers explicitly to ensure that it operates correctly.
See the Instantiation table in Instantiation for details on peripherals and their IDs.
The UARTE implements EasyDMA for reading and writing to and from the RAM.
If the TXD.PTR and the RXD.PTR are not pointing to the Data RAM region, an EasyDMA transfer may result in a HardFault or RAM corruption. See Memory for more information about the different memory regions.
The .PTR and .MAXCNT registers are double-buffered. They can be updated and prepared for the next RX/TX transmission immediately after having received the RXSTARTED/TXSTARTED event.
The ENDRX/ENDTX event indicates that EasyDMA has finished accessing respectively the RX/TX buffer in RAM.
The first step of a DMA transmission is storing bytes in the transmit buffer and configuring EasyDMA. This is achieved by writing the initial address pointer to TXD.PTR, and the number of bytes in the RAM buffer to TXD.MAXCNT. The UARTE transmission is started by triggering the STARTTX task.
After each byte has been sent over the TXD line, a TXDRDY event will be generated.
When all bytes in the TXD buffer, as specified in the TXD.MAXCNT register, have been transmitted, the UARTE transmission will end automatically and an ENDTX event will be generated.
A UARTE transmission sequence is stopped by triggering the STOPTX task, a TXSTOPPED event will be generated when the UARTE transmitter has stopped.
If the ENDTX event has not already been generated when the UARTE transmitter has come to a stop, the UARTE will generate the ENDTX event explicitly even though all bytes in the TXD buffer, as specified in the TXD.MAXCNT register, have not been transmitted.
If flow control is enabled, a transmission will be automatically suspended when CTS is deactivated and resumed when CTS is activated again, as illustrated in Figure 2. A byte that is in transmission when CTS is deactivated will be fully transmitted before the transmission is suspended.
The UARTE transmitter will be in its lowest activity level, and consume the least amount of energy, when it is stopped, i.e. before it is started via STARTTX or after it has been stopped via STOPTX and the TXSTOPPED event has been generated. See POWER — Power supply for more information about power modes.
The UARTE receiver is started by triggering the STARTRX task. The UARTE receiver is using EasyDMA to store incoming data in an RX buffer in RAM.
The RX buffer is located at the address specified in the RXD.PTR register. The RXD.PTR register is double-buffered and it can be updated and prepared for the next STARTRX task immediately after the RXSTARTED event is generated. The size of the RX buffer is specified in the RXD.MAXCNT register and the UARTE will generate an ENDRX event when it has filled up the RX buffer, see Figure 3.
For each byte received over the RXD line, an RXDRDY event will be generated. This event is likely to occur before the corresponding data has been transferred to Data RAM.
The RXD.AMOUNT register can be queried following an ENDRX event to see how many new bytes have been transferred to the RX buffer in RAM since the previous ENDRX event.
The UARTE receiver is stopped by triggering the STOPRX task. An RXTO event is generated when the UARTE has stopped. The UARTE will make sure that an impending ENDRX event will be generated before the RXTO event is generated. This means that the UARTE will guarantee that no ENDRX event will be generated after RXTO, unless the UARTE is restarted or a FLUSHRX command is issued after the RXTO event is generated.
To be able to know how many bytes have actually been received into the RX buffer, the CPU can read the RXD.AMOUNT register following the ENDRX event or the RXTO event.
The UARTE is able to receive up to four bytes after the STOPRX task has been triggered as long as these are sent in succession immediately after the RTS signal is deactivated. This is possible because after the RTS is deactivated the UARTE is able to receive bytes for an extended period equal to the time it takes to send 4 bytes on the configured baud rate.
After the RXTO event is generated the internal RX FIFO may still contain data, and to move this data to RAM the FLUSHRX task must be triggered. To make sure that this data does not overwrite data in the RX buffer, the RX buffer should be emptied or the RXD.PTR should be updated before the FLUSHRX task is triggered. To make sure that all data in the RX FIFO is moved to the RX buffer, the RXD.MAXCNT register must be set to RXD.MAXCNT > 4, see Figure 4. The UARTE will generate the ENDRX event after completing the FLUSHRX task even if the RX FIFO was empty or if the RX buffer does not get filled up. To be able to know how many bytes have actually been received into the RX buffer in this case, the CPU can read the RXD.AMOUNT register following the ENDRX event.
If HW flow control is enabled the RTS signal will be deactivated when the receiver is stopped via the STOPRX task or when the UARTE is only able to receive four more bytes in its internal RX FIFO.
With flow control disabled, the UARTE will function in the same way as when the flow control is enabled except that the RTS line will not be used. This means that no signal will be generated when the UARTE has reached the point where it is only able to receive four more bytes in its internal RX FIFO. Data received when the internal RX FIFO is filled up, will be lost.
The UARTE receiver will be in its lowest activity level, and consume the least amount of energy, when it is stopped, i.e. before it is started via STARTRX or after it has been stopped via STOPRX and the RXTO event has been generated. See POWER — Power supply for more information about power modes.
An ERROR event, in the form of a framing error, will be generated if a valid stop bit is not detected in a frame. Another ERROR event, in the form of a break condition, will be generated if the RXD line is held active low for longer than the length of a data frame. Effectively, a framing error is always generated before a break condition occurs.
An ERROR event will not stop reception. If the error was a parity error, the received byte will still be transferred into Data RAM, and so will following incoming bytes. If there was a framing error (wrong stop bit), that specific byte will NOT be stored into Data RAM, but following incoming bytes will.
If flow control is not enabled, the interface will behave as if the CTS and RTS lines are kept active all the time.
When parity is enabled, the parity will be generated automatically from the even parity of TXD and RXD for transmission and reception respectively.
When putting the system in low power and the peripheral is not needed, lowest possible power consumption is achieved by stopping, and then disabling the peripheral.
The STOPTX and STOPRX tasks may not be always needed (the peripheral might already be stopped), but if STOPTX and/or STOPRX is sent, software shall wait until the TXSTOPPED and/or RXTO event is received in response, before disabling the peripheral through the ENABLE register.
The different signals RXD, CTS (Clear To Send, active low), RTS (Request To Send, active low), and TXD associated with the UARTE are mapped to physical pins according to the configuration specified in the PSEL.RXD, PSEL.CTS, PSEL.RTS, and PSEL.TXD registers respectively.
The PSEL.RXD, PSEL.CTS, PSEL.RTS, and PSEL.TXD registers and their configurations are only used as long as the UARTE is enabled, and retained only for the duration the device is in ON mode. PSEL.RXD, PSEL.RTS, PSEL.RTS and PSEL.TXD must only be configured when the UARTE is disabled.
To secure correct signal levels on the pins by the UARTE when the system is in OFF mode, the pins must be configured in the GPIO peripheral as described in Table 1.
Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in unpredictable behavior.
UARTE signal | UARTE pin | Direction | Output value |
---|---|---|---|
RXD | As specified in PSEL.RXD | Input | Not applicable |
CTS | As specified in PSEL.CTS | Input | Not applicable |
RTS | As specified in PSEL.RTS | Output | 1 |
TXD | As specified in PSEL.TXD | Output | 1 |
Base address | Peripheral | Instance | Description | Configuration | |
---|---|---|---|---|---|
0x40002000 | UARTE | UARTE0 |
Universal Asynchronous Receiver/Transmitter with EasyDMA |
Register | Offset | Description | |
---|---|---|---|
TASKS_STARTRX | 0x000 |
Start UART receiver |
|
TASKS_STOPRX | 0x004 |
Stop UART receiver |
|
TASKS_STARTTX | 0x008 |
Start UART transmitter |
|
TASKS_STOPTX | 0x00C |
Stop UART transmitter |
|
TASKS_FLUSHRX | 0x02C |
Flush RX FIFO into RX buffer |
|
EVENTS_CTS | 0x100 |
CTS is activated (set low). Clear To Send. |
|
EVENTS_NCTS | 0x104 |
CTS is deactivated (set high). Not Clear To Send. |
|
EVENTS_RXDRDY | 0x108 |
Data received in RXD (but potentially not yet transferred to Data RAM) |
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EVENTS_ENDRX | 0x110 |
Receive buffer is filled up |
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EVENTS_TXDRDY | 0x11C |
Data sent from TXD |
|
EVENTS_ENDTX | 0x120 |
Last TX byte transmitted |
|
EVENTS_ERROR | 0x124 |
Error detected |
|
EVENTS_RXTO | 0x144 |
Receiver timeout |
|
EVENTS_RXSTARTED | 0x14C |
UART receiver has started |
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EVENTS_TXSTARTED | 0x150 |
UART transmitter has started |
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EVENTS_TXSTOPPED | 0x158 |
Transmitter stopped |
|
SHORTS | 0x200 |
Shortcut register |
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INTEN | 0x300 |
Enable or disable interrupt |
|
INTENSET | 0x304 |
Enable interrupt |
|
INTENCLR | 0x308 |
Disable interrupt |
|
ERRORSRC | 0x480 |
Error source |
|
ENABLE | 0x500 |
Enable UART |
|
PSEL.RTS | 0x508 |
Pin select for RTS signal |
|
PSEL.TXD | 0x50C |
Pin select for TXD signal |
|
PSEL.CTS | 0x510 |
Pin select for CTS signal |
|
PSEL.RXD | 0x514 |
Pin select for RXD signal |
|
BAUDRATE | 0x524 |
Baud rate. Accuracy depends on the HFCLK source selected. |
|
RXD.PTR | 0x534 |
Data pointer |
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RXD.MAXCNT | 0x538 |
Maximum number of bytes in receive buffer |
|
RXD.AMOUNT | 0x53C |
Number of bytes transferred in the last transaction |
|
TXD.PTR | 0x544 |
Data pointer |
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TXD.MAXCNT | 0x548 |
Maximum number of bytes in transmit buffer |
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TXD.AMOUNT | 0x54C |
Number of bytes transferred in the last transaction |
|
CONFIG | 0x56C |
Configuration of parity and hardware flow control |
Address offset: 0x200
Shortcut register
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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Id | D | C | |||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
C | RW |
ENDRX_STARTRX |
Shortcut between ENDRX event and STARTRX task See EVENTS_ENDRX and TASKS_STARTRX |
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Disabled |
0 |
Disable shortcut |
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Enabled |
1 |
Enable shortcut |
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D | RW |
ENDRX_STOPRX |
Shortcut between ENDRX event and STOPRX task See EVENTS_ENDRX and TASKS_STOPRX |
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Disabled |
0 |
Disable shortcut |
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Enabled |
1 |
Enable shortcut |
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Address offset: 0x300
Enable or disable interrupt
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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Id | L | J | I | H | G | F | E | D | C | B | A | ||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
CTS |
Enable or disable interrupt for CTS event See EVENTS_CTS |
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Disabled |
0 |
Disable |
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Enabled |
1 |
Enable |
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B | RW |
NCTS |
Enable or disable interrupt for NCTS event See EVENTS_NCTS |
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Disabled |
0 |
Disable |
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Enabled |
1 |
Enable |
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C | RW |
RXDRDY |
Enable or disable interrupt for RXDRDY event See EVENTS_RXDRDY |
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Disabled |
0 |
Disable |
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Enabled |
1 |
Enable |
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D | RW |
ENDRX |
Enable or disable interrupt for ENDRX event See EVENTS_ENDRX |
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Disabled |
0 |
Disable |
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Enabled |
1 |
Enable |
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E | RW |
TXDRDY |
Enable or disable interrupt for TXDRDY event See EVENTS_TXDRDY |
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Disabled |
0 |
Disable |
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Enabled |
1 |
Enable |
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F | RW |
ENDTX |
Enable or disable interrupt for ENDTX event See EVENTS_ENDTX |
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Disabled |
0 |
Disable |
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Enabled |
1 |
Enable |
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G | RW |
ERROR |
Enable or disable interrupt for ERROR event See EVENTS_ERROR |
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Disabled |
0 |
Disable |
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Enabled |
1 |
Enable |
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H | RW |
RXTO |
Enable or disable interrupt for RXTO event See EVENTS_RXTO |
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Disabled |
0 |
Disable |
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Enabled |
1 |
Enable |
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I | RW |
RXSTARTED |
Enable or disable interrupt for RXSTARTED event See EVENTS_RXSTARTED |
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Disabled |
0 |
Disable |
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Enabled |
1 |
Enable |
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J | RW |
TXSTARTED |
Enable or disable interrupt for TXSTARTED event See EVENTS_TXSTARTED |
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Disabled |
0 |
Disable |
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Enabled |
1 |
Enable |
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L | RW |
TXSTOPPED |
Enable or disable interrupt for TXSTOPPED event See EVENTS_TXSTOPPED |
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Disabled |
0 |
Disable |
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Enabled |
1 |
Enable |
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Address offset: 0x304
Enable interrupt
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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Id | L | J | I | H | G | F | E | D | C | B | A | ||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
CTS |
Write '1' to Enable interrupt for CTS event See EVENTS_CTS |
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Set |
1 |
Enable |
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Disabled |
0 |
Read: Disabled |
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Enabled |
1 |
Read: Enabled |
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B | RW |
NCTS |
Write '1' to Enable interrupt for NCTS event See EVENTS_NCTS |
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Set |
1 |
Enable |
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Disabled |
0 |
Read: Disabled |
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Enabled |
1 |
Read: Enabled |
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C | RW |
RXDRDY |
Write '1' to Enable interrupt for RXDRDY event See EVENTS_RXDRDY |
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Set |
1 |
Enable |
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Disabled |
0 |
Read: Disabled |
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Enabled |
1 |
Read: Enabled |
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D | RW |
ENDRX |
Write '1' to Enable interrupt for ENDRX event See EVENTS_ENDRX |
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Set |
1 |
Enable |
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Disabled |
0 |
Read: Disabled |
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Enabled |
1 |
Read: Enabled |
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E | RW |
TXDRDY |
Write '1' to Enable interrupt for TXDRDY event See EVENTS_TXDRDY |
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Set |
1 |
Enable |
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Disabled |
0 |
Read: Disabled |
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Enabled |
1 |
Read: Enabled |
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F | RW |
ENDTX |
Write '1' to Enable interrupt for ENDTX event See EVENTS_ENDTX |
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Set |
1 |
Enable |
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Disabled |
0 |
Read: Disabled |
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Enabled |
1 |
Read: Enabled |
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G | RW |
ERROR |
Write '1' to Enable interrupt for ERROR event See EVENTS_ERROR |
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Set |
1 |
Enable |
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Disabled |
0 |
Read: Disabled |
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Enabled |
1 |
Read: Enabled |
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H | RW |
RXTO |
Write '1' to Enable interrupt for RXTO event See EVENTS_RXTO |
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Set |
1 |
Enable |
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Disabled |
0 |
Read: Disabled |
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Enabled |
1 |
Read: Enabled |
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I | RW |
RXSTARTED |
Write '1' to Enable interrupt for RXSTARTED event See EVENTS_RXSTARTED |
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Set |
1 |
Enable |
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Disabled |
0 |
Read: Disabled |
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Enabled |
1 |
Read: Enabled |
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J | RW |
TXSTARTED |
Write '1' to Enable interrupt for TXSTARTED event See EVENTS_TXSTARTED |
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Set |
1 |
Enable |
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Disabled |
0 |
Read: Disabled |
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Enabled |
1 |
Read: Enabled |
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L | RW |
TXSTOPPED |
Write '1' to Enable interrupt for TXSTOPPED event See EVENTS_TXSTOPPED |
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Set |
1 |
Enable |
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Disabled |
0 |
Read: Disabled |
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Enabled |
1 |
Read: Enabled |
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Address offset: 0x308
Disable interrupt
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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Id | L | J | I | H | G | F | E | D | C | B | A | ||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
CTS |
Write '1' to Disable interrupt for CTS event See EVENTS_CTS |
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Clear |
1 |
Disable |
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Disabled |
0 |
Read: Disabled |
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Enabled |
1 |
Read: Enabled |
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B | RW |
NCTS |
Write '1' to Disable interrupt for NCTS event See EVENTS_NCTS |
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Clear |
1 |
Disable |
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Disabled |
0 |
Read: Disabled |
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Enabled |
1 |
Read: Enabled |
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C | RW |
RXDRDY |
Write '1' to Disable interrupt for RXDRDY event See EVENTS_RXDRDY |
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Clear |
1 |
Disable |
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Disabled |
0 |
Read: Disabled |
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Enabled |
1 |
Read: Enabled |
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D | RW |
ENDRX |
Write '1' to Disable interrupt for ENDRX event See EVENTS_ENDRX |
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Clear |
1 |
Disable |
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Disabled |
0 |
Read: Disabled |
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Enabled |
1 |
Read: Enabled |
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E | RW |
TXDRDY |
Write '1' to Disable interrupt for TXDRDY event See EVENTS_TXDRDY |
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Clear |
1 |
Disable |
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Disabled |
0 |
Read: Disabled |
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Enabled |
1 |
Read: Enabled |
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F | RW |
ENDTX |
Write '1' to Disable interrupt for ENDTX event See EVENTS_ENDTX |
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Clear |
1 |
Disable |
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Disabled |
0 |
Read: Disabled |
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Enabled |
1 |
Read: Enabled |
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G | RW |
ERROR |
Write '1' to Disable interrupt for ERROR event See EVENTS_ERROR |
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Clear |
1 |
Disable |
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Disabled |
0 |
Read: Disabled |
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Enabled |
1 |
Read: Enabled |
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H | RW |
RXTO |
Write '1' to Disable interrupt for RXTO event See EVENTS_RXTO |
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Clear |
1 |
Disable |
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Disabled |
0 |
Read: Disabled |
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Enabled |
1 |
Read: Enabled |
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I | RW |
RXSTARTED |
Write '1' to Disable interrupt for RXSTARTED event See EVENTS_RXSTARTED |
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Clear |
1 |
Disable |
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Disabled |
0 |
Read: Disabled |
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Enabled |
1 |
Read: Enabled |
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J | RW |
TXSTARTED |
Write '1' to Disable interrupt for TXSTARTED event See EVENTS_TXSTARTED |
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Clear |
1 |
Disable |
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Disabled |
0 |
Read: Disabled |
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Enabled |
1 |
Read: Enabled |
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L | RW |
TXSTOPPED |
Write '1' to Disable interrupt for TXSTOPPED event See EVENTS_TXSTOPPED |
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Clear |
1 |
Disable |
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Disabled |
0 |
Read: Disabled |
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Enabled |
1 |
Read: Enabled |
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Address offset: 0x480
Error source
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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Id | D | C | B | A | |||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
OVERRUN |
Overrun error A start bit is received while the previous data still lies in RXD. (Previous data is lost.) |
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NotPresent |
0 |
Read: error not present |
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Present |
1 |
Read: error present |
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B | RW |
PARITY |
Parity error A character with bad parity is received, if HW parity check is enabled. |
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NotPresent |
0 |
Read: error not present |
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Present |
1 |
Read: error present |
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C | RW |
FRAMING |
Framing error occurred A valid stop bit is not detected on the serial data input after all bits in a character have been received. |
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NotPresent |
0 |
Read: error not present |
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Present |
1 |
Read: error present |
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D | RW |
BREAK |
Break condition The serial data input is '0' for longer than the length of a data frame. (The data frame length is 10 bits without parity bit, and 11 bits with parity bit.). |
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NotPresent |
0 |
Read: error not present |
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Present |
1 |
Read: error present |
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Address offset: 0x500
Enable UART
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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Id | A | A | A | A | |||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
ENABLE |
Enable or disable UARTE |
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Disabled |
0 |
Disable UARTE |
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Enabled |
8 |
Enable UARTE |
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Address offset: 0x508
Pin select for RTS signal
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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Id | B | A | A | A | A | A | |||||||||||||||||||||||||||||
Reset 0xFFFFFFFF | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
PIN |
[0..31] |
Pin number |
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B | RW |
CONNECT |
Connection |
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Disconnected |
1 |
Disconnect |
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Connected |
0 |
Connect |
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Address offset: 0x50C
Pin select for TXD signal
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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Id | B | A | A | A | A | A | |||||||||||||||||||||||||||||
Reset 0xFFFFFFFF | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
PIN |
[0..31] |
Pin number |
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B | RW |
CONNECT |
Connection |
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Disconnected |
1 |
Disconnect |
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Connected |
0 |
Connect |
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Address offset: 0x510
Pin select for CTS signal
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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Id | B | A | A | A | A | A | |||||||||||||||||||||||||||||
Reset 0xFFFFFFFF | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
PIN |
[0..31] |
Pin number |
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B | RW |
CONNECT |
Connection |
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Disconnected |
1 |
Disconnect |
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Connected |
0 |
Connect |
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Address offset: 0x514
Pin select for RXD signal
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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Id | B | A | A | A | A | A | |||||||||||||||||||||||||||||
Reset 0xFFFFFFFF | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
PIN |
[0..31] |
Pin number |
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B | RW |
CONNECT |
Connection |
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Disconnected |
1 |
Disconnect |
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Connected |
0 |
Connect |
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Address offset: 0x524
Baud rate. Accuracy depends on the HFCLK source selected.
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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Id | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | |||
Reset 0x04000000 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
BAUDRATE |
Baud rate |
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Baud1200 |
0x0004F000 |
1200 baud (actual rate: 1205) |
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Baud2400 |
0x0009D000 |
2400 baud (actual rate: 2396) |
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Baud4800 |
0x0013B000 |
4800 baud (actual rate: 4808) |
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Baud9600 |
0x00275000 |
9600 baud (actual rate: 9598) |
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Baud14400 |
0x003AF000 |
14400 baud (actual rate: 14401) |
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Baud19200 |
0x004EA000 |
19200 baud (actual rate: 19208) |
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Baud28800 |
0x0075C000 |
28800 baud (actual rate: 28777) |
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Baud38400 |
0x009D0000 |
38400 baud (actual rate: 38369) |
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Baud57600 |
0x00EB0000 |
57600 baud (actual rate: 57554) |
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Baud76800 |
0x013A9000 |
76800 baud (actual rate: 76923) |
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Baud115200 |
0x01D60000 |
115200 baud (actual rate: 115108) |
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Baud230400 |
0x03B00000 |
230400 baud (actual rate: 231884) |
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Baud250000 |
0x04000000 |
250000 baud |
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Baud460800 |
0x07400000 |
460800 baud (actual rate: 457143) |
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Baud921600 |
0x0F000000 |
921600 baud (actual rate: 941176) |
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Baud1M |
0x10000000 |
1Mega baud |
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Address offset: 0x534
Data pointer
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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Id | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | |||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
PTR |
Data pointer |
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Address offset: 0x538
Maximum number of bytes in receive buffer
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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Id | A | A | A | A | A | A | A | A | |||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
MAXCNT |
Maximum number of bytes in receive buffer |
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Address offset: 0x53C
Number of bytes transferred in the last transaction
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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Id | A | A | A | A | A | A | A | A | |||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | R |
AMOUNT |
Number of bytes transferred in the last transaction |
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Address offset: 0x544
Data pointer
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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Id | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | |||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
PTR |
Data pointer |
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Address offset: 0x548
Maximum number of bytes in transmit buffer
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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Id | A | A | A | A | A | A | A | A | |||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
MAXCNT |
Maximum number of bytes in transmit buffer |
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Address offset: 0x54C
Number of bytes transferred in the last transaction
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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Id | A | A | A | A | A | A | A | A | |||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | R |
AMOUNT |
Number of bytes transferred in the last transaction |
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Address offset: 0x56C
Configuration of parity and hardware flow control
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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Id | B | B | B | A | |||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
HWFC |
Hardware flow control |
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Disabled |
0 |
Disabled |
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Enabled |
1 |
Enabled |
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B | RW |
PARITY |
Parity |
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Excluded |
0x0 |
Exclude parity bit |
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Included |
0x7 |
Include parity bit |
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Symbol | Description | Min. | Typ. | Max. | Units | ||||
---|---|---|---|---|---|---|---|---|---|
fUARTE |
Baud rate for UARTE1. |
1000 | kbps | ||||||
IUARTE1M |
Run current at max baud rate. |
55 | µA | ||||||
IUARTE115k |
Run current at 115200 bps. |
55 | µA | ||||||
IUARTE1k2 |
Run current at 1200 bps. |
55 | µA | ||||||
IUARTE,IDLE |
Idle current for UARTE (STARTed, no XXX activity) |
1 | µA | ||||||
tUARTE,CTSH |
CTS high time |
1 | µs | ||||||
tUARTE,START,LP |
Time from STARTRX/STARTTX task to transmission started, low power mode |
tUARTE,START,CL + tSTART_HFINT | µs | ||||||
tUARTE,START,CL |
Time from STARTRX/STARTTX task to transmission started, constant latency mode |
1 | µs |