GPIOTE — GPIO tasks and events

The GPIO tasks and events (GPIOTE) module provides functionality for accessing GPIO pins using tasks and events. Each GPIOTE channel can be assigned to one pin.

A GPIOTE block enables GPIOs to generate events on pin state change which can be used to carry out tasks through the PPI system. A GPIO can also be driven to change state on system events using the PPI system. Low power detection of pin state changes is possible when in System ON or System OFF.

Table 1. GPIOTE properties
Instance Number of GPIOTE channels
GPIOTE 8

Up to three tasks can be used in each GPIOTE channel for performing write operations to a pin. Two tasks are fixed (SET and CLR), and one (OUT) is configurable to perform following operations:

An event can be generated in each GPIOTE channel from one of the following input conditions:

Pin events and tasks

The GPIOTE module has a number of tasks and events that can be configured to operate on individual GPIO pins.

The tasks (SET[n], CLR[n] and OUT[n]) can be used for writing to individual pins, and the events (IN[n]) can be generated from changes occurring at the inputs of individual pins.

The SET task will set the pin selected in CONFIG[n].PSEL to high.

The CLR task will set the pin low.

The effect of the OUT task on the pin is configurable in CONFIG[n].POLARITY , and can either set the pin high, set it low, or toggle it.

The tasks and events are configured using the CONFIG[n] registers. Every set of SET, CLR and OUT[n] tasks and IN[n] events has one CONFIG[n] register associated with it.

As long as a SET[n], CLR[n] and OUT[n] task or an IN[n] event is configured to control a pin n, the pin's output value will only be updated by the GPIOTE module. The pin's output value as specified in the GPIO will therefore be ignored as long as the pin is controlled by GPIOTE. Attempting to write a pin as a normal GPIO pin will have no effect. When the GPIOTE is disconnected from a pin, see MODE field in CONFIG[n] register, the associated pin will get the output and configuration values specified in the GPIO module.

When conflicting tasks are triggered simultaneously (i.e. during the same clock cycle) in one channel, the precedence of the tasks will be as described in Table 2.

Table 2. Task priorities
Priority Task
1 OUT
2 CLR
3 SET

When setting the CONFIG[n] registers, MODE=Disabled does not have the same effect as MODE=Task and POLARITY=None. In the latter case, a CLR or SET task occurring at the exact same time as OUT will end up with no change on the pin, according to the priorities described in the table above.

When a GPIOTE channel is configured to operate on a pin as a task, the initial value of that pin is configured in the OUTINIT field of CONFIG[n].

Port event

PORT is an event that can be generated from multiple input pins using the GPIO DETECT signal.

The event will be generated on the rising edge of the DETECT signal. See GPIO — General purpose input/output for more information about the DETECT signal.

Putting the system into System ON IDLE while DETECT is high will not cause DETECT to wake the system up again. Make sure to clear all DETECT sources before entering sleep. If the LATCH register is used as a source, if any bit in LATCH is still high after clearing all or part of the register (for instance due to one of the PINx.DETECT signal still high), a new rising edge will be generated on DETECT, see Pin configuration.

Trying to put the system to System OFF while DETECT is high will cause a wakeup from System OFF reset.

This feature is always enabled although the peripheral itself appears to be IDLE, that is, no clocks or other power intensive infrastructure have to be requested to keep this feature enabled. This feature can therefore be used to wake up the CPU from a WFI or WFE type sleep in System ON with all peripherals and the CPU idle, that is, lowest power consumption in System ON mode.

In order to prevent spurious interrupts from the PORT event while configuring the sources, the user shall first disable interrupts on the PORT event (through INTENCLR.PORT), then configure the sources (PIN_CNF[n].SENSE), clear any potential event that could have occurred during configuration (write '1' to EVENTS_PORT), and finally enable interrupts (through INTENSET.PORT).

Tasks and events pin configuration

Each GPIOTE channel is associated with one physical GPIO pin through the CONFIG.PSEL field.

When Event mode is selected in CONFIG.MODE, the pin specified by CONFIG.PSEL will be configured as an input, overriding the DIR setting in GPIO. Similarly, when Task mode is selected in CONFIG.MODE, the pin specified by CONFIG.PSEL will be configured as an output overriding the DIR setting and OUT value in GPIO. When Disabled is selected in CONFIG.MODE, the pin specified by CONFIG.PSEL will use its configuration from the PIN[n].CNF registers in GPIO.

Only one GPIOTE channel can be assigned to one physical pin. Failing to do so may result in unpredictable behavior.

Registers

Table 3. Instances
Base address Peripheral Instance Description Configuration
0x40006000 GPIOTE GPIOTE

GPIO Tasks and Events

   
Table 4. Register Overview
Register Offset Description
TASKS_OUT[0] 0x000

Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY.

 
TASKS_OUT[1] 0x004

Task for writing to pin specified in CONFIG[1].PSEL. Action on pin is configured in CONFIG[1].POLARITY.

 
TASKS_OUT[2] 0x008

Task for writing to pin specified in CONFIG[2].PSEL. Action on pin is configured in CONFIG[2].POLARITY.

 
TASKS_OUT[3] 0x00C

Task for writing to pin specified in CONFIG[3].PSEL. Action on pin is configured in CONFIG[3].POLARITY.

 
TASKS_OUT[4] 0x010

Task for writing to pin specified in CONFIG[4].PSEL. Action on pin is configured in CONFIG[4].POLARITY.

 
TASKS_OUT[5] 0x014

Task for writing to pin specified in CONFIG[5].PSEL. Action on pin is configured in CONFIG[5].POLARITY.

 
TASKS_OUT[6] 0x018

Task for writing to pin specified in CONFIG[6].PSEL. Action on pin is configured in CONFIG[6].POLARITY.

 
TASKS_OUT[7] 0x01C

Task for writing to pin specified in CONFIG[7].PSEL. Action on pin is configured in CONFIG[7].POLARITY.

 
TASKS_SET[0] 0x030

Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it high.

 
TASKS_SET[1] 0x034

Task for writing to pin specified in CONFIG[1].PSEL. Action on pin is to set it high.

 
TASKS_SET[2] 0x038

Task for writing to pin specified in CONFIG[2].PSEL. Action on pin is to set it high.

 
TASKS_SET[3] 0x03C

Task for writing to pin specified in CONFIG[3].PSEL. Action on pin is to set it high.

 
TASKS_SET[4] 0x040

Task for writing to pin specified in CONFIG[4].PSEL. Action on pin is to set it high.

 
TASKS_SET[5] 0x044

Task for writing to pin specified in CONFIG[5].PSEL. Action on pin is to set it high.

 
TASKS_SET[6] 0x048

Task for writing to pin specified in CONFIG[6].PSEL. Action on pin is to set it high.

 
TASKS_SET[7] 0x04C

Task for writing to pin specified in CONFIG[7].PSEL. Action on pin is to set it high.

 
TASKS_CLR[0] 0x060

Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it low.

 
TASKS_CLR[1] 0x064

Task for writing to pin specified in CONFIG[1].PSEL. Action on pin is to set it low.

 
TASKS_CLR[2] 0x068

Task for writing to pin specified in CONFIG[2].PSEL. Action on pin is to set it low.

 
TASKS_CLR[3] 0x06C

Task for writing to pin specified in CONFIG[3].PSEL. Action on pin is to set it low.

 
TASKS_CLR[4] 0x070

Task for writing to pin specified in CONFIG[4].PSEL. Action on pin is to set it low.

 
TASKS_CLR[5] 0x074

Task for writing to pin specified in CONFIG[5].PSEL. Action on pin is to set it low.

 
TASKS_CLR[6] 0x078

Task for writing to pin specified in CONFIG[6].PSEL. Action on pin is to set it low.

 
TASKS_CLR[7] 0x07C

Task for writing to pin specified in CONFIG[7].PSEL. Action on pin is to set it low.

 
EVENTS_IN[0] 0x100

Event generated from pin specified in CONFIG[0].PSEL

 
EVENTS_IN[1] 0x104

Event generated from pin specified in CONFIG[1].PSEL

 
EVENTS_IN[2] 0x108

Event generated from pin specified in CONFIG[2].PSEL

 
EVENTS_IN[3] 0x10C

Event generated from pin specified in CONFIG[3].PSEL

 
EVENTS_IN[4] 0x110

Event generated from pin specified in CONFIG[4].PSEL

 
EVENTS_IN[5] 0x114

Event generated from pin specified in CONFIG[5].PSEL

 
EVENTS_IN[6] 0x118

Event generated from pin specified in CONFIG[6].PSEL

 
EVENTS_IN[7] 0x11C

Event generated from pin specified in CONFIG[7].PSEL

 
EVENTS_PORT 0x17C

Event generated from multiple input GPIO pins with SENSE mechanism enabled

 
INTENSET 0x304

Enable interrupt

 
INTENCLR 0x308

Disable interrupt

 
CONFIG[0] 0x510

Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event

 
CONFIG[1] 0x514

Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event

 
CONFIG[2] 0x518

Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event

 
CONFIG[3] 0x51C

Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event

 
CONFIG[4] 0x520

Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event

 
CONFIG[5] 0x524

Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event

 
CONFIG[6] 0x528

Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event

 
CONFIG[7] 0x52C

Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event

 

INTENSET

Address offset: 0x304

Enable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id I                                               H G F E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

IN0

   

Write '1' to Enable interrupt for IN[0] event

See EVENTS_IN[0]

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

B RW

IN1

   

Write '1' to Enable interrupt for IN[1] event

See EVENTS_IN[1]

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

C RW

IN2

   

Write '1' to Enable interrupt for IN[2] event

See EVENTS_IN[2]

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

D RW

IN3

   

Write '1' to Enable interrupt for IN[3] event

See EVENTS_IN[3]

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

E RW

IN4

   

Write '1' to Enable interrupt for IN[4] event

See EVENTS_IN[4]

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

F RW

IN5

   

Write '1' to Enable interrupt for IN[5] event

See EVENTS_IN[5]

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

G RW

IN6

   

Write '1' to Enable interrupt for IN[6] event

See EVENTS_IN[6]

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

H RW

IN7

   

Write '1' to Enable interrupt for IN[7] event

See EVENTS_IN[7]

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

I RW

PORT

   

Write '1' to Enable interrupt for PORT event

See EVENTS_PORT

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

 

INTENCLR

Address offset: 0x308

Disable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id I                                               H G F E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

IN0

   

Write '1' to Disable interrupt for IN[0] event

See EVENTS_IN[0]

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

B RW

IN1

   

Write '1' to Disable interrupt for IN[1] event

See EVENTS_IN[1]

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

C RW

IN2

   

Write '1' to Disable interrupt for IN[2] event

See EVENTS_IN[2]

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

D RW

IN3

   

Write '1' to Disable interrupt for IN[3] event

See EVENTS_IN[3]

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

E RW

IN4

   

Write '1' to Disable interrupt for IN[4] event

See EVENTS_IN[4]

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

F RW

IN5

   

Write '1' to Disable interrupt for IN[5] event

See EVENTS_IN[5]

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

G RW

IN6

   

Write '1' to Disable interrupt for IN[6] event

See EVENTS_IN[6]

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

H RW

IN7

   

Write '1' to Disable interrupt for IN[7] event

See EVENTS_IN[7]

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

I RW

PORT

   

Write '1' to Disable interrupt for PORT event

See EVENTS_PORT

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

 

CONFIG[0]

Address offset: 0x510

Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                       D     C C       B B B B B             A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

MODE

   

Mode

     

Disabled

0

Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module.

     

Event

1

Event mode

The pin specified by PSEL will be configured as an input and the IN[n] event will be generated if operation specified in POLARITY occurs on the pin.

     

Task

3

Task mode

The GPIO specified by PSEL will be configured as an output and triggering the SET[n], CLR[n] or OUT[n] task will perform the operation specified by POLARITY on the pin. When enabled as a task the GPIOTE module will acquire the pin and the pin can no longer be written as a regular output pin from the GPIO module.

B RW

PSEL

 

[0..31]

GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event

C RW

POLARITY

   

When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.

     

None

0

Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity.

     

LoToHi

1

Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin.

     

HiToLo

2

Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin.

     

Toggle

3

Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin.

D RW

OUTINIT

   

When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.

     

Low

0

Task mode: Initial value of pin before task triggering is low

     

High

1

Task mode: Initial value of pin before task triggering is high

 

CONFIG[1]

Address offset: 0x514

Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                       D     C C       B B B B B             A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

MODE

   

Mode

     

Disabled

0

Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module.

     

Event

1

Event mode

The pin specified by PSEL will be configured as an input and the IN[n] event will be generated if operation specified in POLARITY occurs on the pin.

     

Task

3

Task mode

The GPIO specified by PSEL will be configured as an output and triggering the SET[n], CLR[n] or OUT[n] task will perform the operation specified by POLARITY on the pin. When enabled as a task the GPIOTE module will acquire the pin and the pin can no longer be written as a regular output pin from the GPIO module.

B RW

PSEL

 

[0..31]

GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event

C RW

POLARITY

   

When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.

     

None

0

Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity.

     

LoToHi

1

Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin.

     

HiToLo

2

Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin.

     

Toggle

3

Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin.

D RW

OUTINIT

   

When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.

     

Low

0

Task mode: Initial value of pin before task triggering is low

     

High

1

Task mode: Initial value of pin before task triggering is high

 

CONFIG[2]

Address offset: 0x518

Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                       D     C C       B B B B B             A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

MODE

   

Mode

     

Disabled

0

Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module.

     

Event

1

Event mode

The pin specified by PSEL will be configured as an input and the IN[n] event will be generated if operation specified in POLARITY occurs on the pin.

     

Task

3

Task mode

The GPIO specified by PSEL will be configured as an output and triggering the SET[n], CLR[n] or OUT[n] task will perform the operation specified by POLARITY on the pin. When enabled as a task the GPIOTE module will acquire the pin and the pin can no longer be written as a regular output pin from the GPIO module.

B RW

PSEL

 

[0..31]

GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event

C RW

POLARITY

   

When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.

     

None

0

Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity.

     

LoToHi

1

Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin.

     

HiToLo

2

Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin.

     

Toggle

3

Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin.

D RW

OUTINIT

   

When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.

     

Low

0

Task mode: Initial value of pin before task triggering is low

     

High

1

Task mode: Initial value of pin before task triggering is high

 

CONFIG[3]

Address offset: 0x51C

Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                       D     C C       B B B B B             A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

MODE

   

Mode

     

Disabled

0

Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module.

     

Event

1

Event mode

The pin specified by PSEL will be configured as an input and the IN[n] event will be generated if operation specified in POLARITY occurs on the pin.

     

Task

3

Task mode

The GPIO specified by PSEL will be configured as an output and triggering the SET[n], CLR[n] or OUT[n] task will perform the operation specified by POLARITY on the pin. When enabled as a task the GPIOTE module will acquire the pin and the pin can no longer be written as a regular output pin from the GPIO module.

B RW

PSEL

 

[0..31]

GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event

C RW

POLARITY

   

When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.

     

None

0

Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity.

     

LoToHi

1

Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin.

     

HiToLo

2

Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin.

     

Toggle

3

Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin.

D RW

OUTINIT

   

When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.

     

Low

0

Task mode: Initial value of pin before task triggering is low

     

High

1

Task mode: Initial value of pin before task triggering is high

 

CONFIG[4]

Address offset: 0x520

Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                       D     C C       B B B B B             A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

MODE

   

Mode

     

Disabled

0

Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module.

     

Event

1

Event mode

The pin specified by PSEL will be configured as an input and the IN[n] event will be generated if operation specified in POLARITY occurs on the pin.

     

Task

3

Task mode

The GPIO specified by PSEL will be configured as an output and triggering the SET[n], CLR[n] or OUT[n] task will perform the operation specified by POLARITY on the pin. When enabled as a task the GPIOTE module will acquire the pin and the pin can no longer be written as a regular output pin from the GPIO module.

B RW

PSEL

 

[0..31]

GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event

C RW

POLARITY

   

When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.

     

None

0

Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity.

     

LoToHi

1

Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin.

     

HiToLo

2

Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin.

     

Toggle

3

Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin.

D RW

OUTINIT

   

When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.

     

Low

0

Task mode: Initial value of pin before task triggering is low

     

High

1

Task mode: Initial value of pin before task triggering is high

 

CONFIG[5]

Address offset: 0x524

Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                       D     C C       B B B B B             A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

MODE

   

Mode

     

Disabled

0

Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module.

     

Event

1

Event mode

The pin specified by PSEL will be configured as an input and the IN[n] event will be generated if operation specified in POLARITY occurs on the pin.

     

Task

3

Task mode

The GPIO specified by PSEL will be configured as an output and triggering the SET[n], CLR[n] or OUT[n] task will perform the operation specified by POLARITY on the pin. When enabled as a task the GPIOTE module will acquire the pin and the pin can no longer be written as a regular output pin from the GPIO module.

B RW

PSEL

 

[0..31]

GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event

C RW

POLARITY

   

When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.

     

None

0

Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity.

     

LoToHi

1

Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin.

     

HiToLo

2

Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin.

     

Toggle

3

Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin.

D RW

OUTINIT

   

When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.

     

Low

0

Task mode: Initial value of pin before task triggering is low

     

High

1

Task mode: Initial value of pin before task triggering is high

 

CONFIG[6]

Address offset: 0x528

Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                       D     C C       B B B B B             A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

MODE

   

Mode

     

Disabled

0

Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module.

     

Event

1

Event mode

The pin specified by PSEL will be configured as an input and the IN[n] event will be generated if operation specified in POLARITY occurs on the pin.

     

Task

3

Task mode

The GPIO specified by PSEL will be configured as an output and triggering the SET[n], CLR[n] or OUT[n] task will perform the operation specified by POLARITY on the pin. When enabled as a task the GPIOTE module will acquire the pin and the pin can no longer be written as a regular output pin from the GPIO module.

B RW

PSEL

 

[0..31]

GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event

C RW

POLARITY

   

When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.

     

None

0

Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity.

     

LoToHi

1

Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin.

     

HiToLo

2

Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin.

     

Toggle

3

Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin.

D RW

OUTINIT

   

When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.

     

Low

0

Task mode: Initial value of pin before task triggering is low

     

High

1

Task mode: Initial value of pin before task triggering is high

 

CONFIG[7]

Address offset: 0x52C

Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                       D     C C       B B B B B             A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

MODE

   

Mode

     

Disabled

0

Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module.

     

Event

1

Event mode

The pin specified by PSEL will be configured as an input and the IN[n] event will be generated if operation specified in POLARITY occurs on the pin.

     

Task

3

Task mode

The GPIO specified by PSEL will be configured as an output and triggering the SET[n], CLR[n] or OUT[n] task will perform the operation specified by POLARITY on the pin. When enabled as a task the GPIOTE module will acquire the pin and the pin can no longer be written as a regular output pin from the GPIO module.

B RW

PSEL

 

[0..31]

GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event

C RW

POLARITY

   

When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.

     

None

0

Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity.

     

LoToHi

1

Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin.

     

HiToLo

2

Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin.

     

Toggle

3

Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin.

D RW

OUTINIT

   

When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.

     

Low

0

Task mode: Initial value of pin before task triggering is low

     

High

1

Task mode: Initial value of pin before task triggering is high

 

Electrical specification

GPIOTE Electrical Specification

Symbol Description Min. Typ. Max. Units
IGPIOTE,IN

Run current with 1 or more GPIOTE active channels in Input mode

0.1 0.5 µA

Documentation feedback | Developer Zone | Updated 2017-02-09