The comparator (COMP) compares an input voltage (VIN+) against a second input voltage (VIN-). VIN+ can be derived from an analog input pin (AIN0-AIN7). VIN- can be derived from multiple sources depending on the operation mode of the comparator.
Main features of the comparator are:
Once enabled (using the ENABLE register), the comparator is started by triggering the START task and stopped by triggering the STOP task. After a start-up time of tCOMP,START, the comparator will generate a READY event to indicate that it is ready for use and that its output is correct. When the COMP module is started, events will be generated every time VIN+ crosses VIN-.
The comparator can be configured to operate in two main operation modes, differential mode and single-ended mode. See the MODE register for more information. In both operation modes, the comparator can operate in different speed and power consumption modes (low-power, normal and high-speed). High-speed mode will consume more power compared to low-power mode, and low-power mode will result in slower response time compared to high-speed mode.
Use the PSEL register to select any of the AIN0-AIN7 pins as VIN+ input, irregardless of the operation mode selected for the comparator. The source of VIN- depends on which operation mode is used:
The selected analog pins will be acquired by the comparator once it is enabled.
An optional hysteresis on VIN+ and VIN- can be enabled when the module is used in differential mode through the HYST register. In single-ended mode, VUP and VDOWN thresholds can be set to implement a hysteresis using the reference ladder (see Figure 4). This hysteresis is in the order of magnitude of 50 mV, and shall prevent noise on the signal to create unwanted events. See Figure 5 for illustration of the effect of an active hysteresis on a noisy input signal.
An upward crossing will generate an UP event and a downward crossing will generate a DOWN event. The CROSS event will be generated every time there is a crossing, independent of direction.
The immediate value of the comparator can be sampled to RESULT register by triggering the SAMPLE task.
In differential mode, the reference input VIN- is derived directly from one of the AINx pins.
Before enabling the comparator via the ENABLE register, the following registers must be configured for the differential mode:
When HYST register is turned on while in this mode, the output of the comparator (and associated events) will change from ABOVE to BELOW whenever VIN+ becomes lower than VIN- - (VDIFFHYST / 2). It will also change from BELOW to ABOVE whenever VIN+ becomes higher than VIN- + (VDIFFHYST / 2). This behavior is illustrated in Figure 3.
In single-ended mode, VIN- is derived from the reference ladder.
Before enabling the comparator via the ENABLE register, the following registers must be configured for the single-ended mode:
The reference ladder uses the reference voltage (VREF) to derive two new voltage references, VUP and VDOWN. VUP and VDOWN are configured using THUP and THDOWN respectively in the TH register. VREF can be derived from any of the available reference sources, configured using the EXTREFSEL and REFSEL registers as illustrated in Figure 4. When AREF is selected in the REFSEL register, the EXTREFSEL register is used to select one of the AIN0-AIN7 analog input pins as reference input. The selected analog pins will be acquired by the comparator once it is enabled.
When the comparator core detects that VIN+ > VIN-, i.e. ABOVE as per the RESULT register, VIN- will switch to VDOWN. When VIN+ falls below VIN- again, VIN- will be switched back to VUP. By specifying VUP larger than VDOWN, a hysteresis can be generated as illustrated in Figure 5 and Figure 6.
Writing to HYST has no effect in single-ended mode, and the content of this register is ignored.
Base address | Peripheral | Instance | Description | Configuration | |
---|---|---|---|---|---|
0x40013000 | COMP | COMP |
General purpose comparator |
Register | Offset | Description | |
---|---|---|---|
TASKS_START | 0x000 |
Start comparator |
|
TASKS_STOP | 0x004 |
Stop comparator |
|
TASKS_SAMPLE | 0x008 |
Sample comparator value |
|
EVENTS_READY | 0x100 |
COMP is ready and output is valid |
|
EVENTS_DOWN | 0x104 |
Downward crossing |
|
EVENTS_UP | 0x108 |
Upward crossing |
|
EVENTS_CROSS | 0x10C |
Downward or upward crossing |
|
SHORTS | 0x200 |
Shortcut register |
|
INTEN | 0x300 |
Enable or disable interrupt |
|
INTENSET | 0x304 |
Enable interrupt |
|
INTENCLR | 0x308 |
Disable interrupt |
|
RESULT | 0x400 |
Compare result |
|
ENABLE | 0x500 |
COMP enable |
|
PSEL | 0x504 |
Pin select |
|
REFSEL | 0x508 |
Reference source select for single-ended mode |
|
EXTREFSEL | 0x50C |
External reference select |
|
TH | 0x530 |
Threshold configuration for hysteresis unit |
|
MODE | 0x534 |
Mode configuration |
|
HYST | 0x538 |
Comparator hysteresis enable |
|
ISOURCE | 0x53C |
Current source select on analog input |
Address offset: 0x200
Shortcut register
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Id | E | D | C | B | A | ||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
READY_SAMPLE |
Shortcut between READY event and SAMPLE task See EVENTS_READY and TASKS_SAMPLE |
||||||||||||||||||||||||||||||||
Disabled |
0 |
Disable shortcut |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Enable shortcut |
|||||||||||||||||||||||||||||||||
B | RW |
READY_STOP |
Shortcut between READY event and STOP task See EVENTS_READY and TASKS_STOP |
||||||||||||||||||||||||||||||||
Disabled |
0 |
Disable shortcut |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Enable shortcut |
|||||||||||||||||||||||||||||||||
C | RW |
DOWN_STOP |
Shortcut between DOWN event and STOP task See EVENTS_DOWN and TASKS_STOP |
||||||||||||||||||||||||||||||||
Disabled |
0 |
Disable shortcut |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Enable shortcut |
|||||||||||||||||||||||||||||||||
D | RW |
UP_STOP |
Shortcut between UP event and STOP task See EVENTS_UP and TASKS_STOP |
||||||||||||||||||||||||||||||||
Disabled |
0 |
Disable shortcut |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Enable shortcut |
|||||||||||||||||||||||||||||||||
E | RW |
CROSS_STOP |
Shortcut between CROSS event and STOP task See EVENTS_CROSS and TASKS_STOP |
||||||||||||||||||||||||||||||||
Disabled |
0 |
Disable shortcut |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Enable shortcut |
|||||||||||||||||||||||||||||||||
Address offset: 0x300
Enable or disable interrupt
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Id | D | C | B | A | |||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
READY |
Enable or disable interrupt for READY event See EVENTS_READY |
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Disabled |
0 |
Disable |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Enable |
|||||||||||||||||||||||||||||||||
B | RW |
DOWN |
Enable or disable interrupt for DOWN event See EVENTS_DOWN |
||||||||||||||||||||||||||||||||
Disabled |
0 |
Disable |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Enable |
|||||||||||||||||||||||||||||||||
C | RW |
UP |
Enable or disable interrupt for UP event See EVENTS_UP |
||||||||||||||||||||||||||||||||
Disabled |
0 |
Disable |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Enable |
|||||||||||||||||||||||||||||||||
D | RW |
CROSS |
Enable or disable interrupt for CROSS event See EVENTS_CROSS |
||||||||||||||||||||||||||||||||
Disabled |
0 |
Disable |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Enable |
|||||||||||||||||||||||||||||||||
Address offset: 0x304
Enable interrupt
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Id | D | C | B | A | |||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
READY |
Write '1' to Enable interrupt for READY event See EVENTS_READY |
||||||||||||||||||||||||||||||||
Set |
1 |
Enable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
B | RW |
DOWN |
Write '1' to Enable interrupt for DOWN event See EVENTS_DOWN |
||||||||||||||||||||||||||||||||
Set |
1 |
Enable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
C | RW |
UP |
Write '1' to Enable interrupt for UP event See EVENTS_UP |
||||||||||||||||||||||||||||||||
Set |
1 |
Enable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
D | RW |
CROSS |
Write '1' to Enable interrupt for CROSS event See EVENTS_CROSS |
||||||||||||||||||||||||||||||||
Set |
1 |
Enable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
Address offset: 0x308
Disable interrupt
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Id | D | C | B | A | |||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
READY |
Write '1' to Disable interrupt for READY event See EVENTS_READY |
||||||||||||||||||||||||||||||||
Clear |
1 |
Disable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
B | RW |
DOWN |
Write '1' to Disable interrupt for DOWN event See EVENTS_DOWN |
||||||||||||||||||||||||||||||||
Clear |
1 |
Disable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
C | RW |
UP |
Write '1' to Disable interrupt for UP event See EVENTS_UP |
||||||||||||||||||||||||||||||||
Clear |
1 |
Disable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
D | RW |
CROSS |
Write '1' to Disable interrupt for CROSS event See EVENTS_CROSS |
||||||||||||||||||||||||||||||||
Clear |
1 |
Disable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
Address offset: 0x400
Compare result
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Id | A | ||||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | R |
RESULT |
Result of last compare. Decision point SAMPLE task. |
||||||||||||||||||||||||||||||||
Below |
0 |
Input voltage is below the threshold (VIN+ < VIN-) |
|||||||||||||||||||||||||||||||||
Above |
1 |
Input voltage is above the threshold (VIN+ > VIN-) |
|||||||||||||||||||||||||||||||||
Address offset: 0x500
COMP enable
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Id | A | A | |||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
ENABLE |
Enable or disable COMP |
||||||||||||||||||||||||||||||||
Disabled |
0 |
Disable |
|||||||||||||||||||||||||||||||||
Enabled |
2 |
Enable |
|||||||||||||||||||||||||||||||||
Address offset: 0x504
Pin select
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Id | A | A | A | ||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
PSEL |
Analog pin select |
||||||||||||||||||||||||||||||||
AnalogInput0 |
0 |
AIN0 selected as analog input |
|||||||||||||||||||||||||||||||||
AnalogInput1 |
1 |
AIN1 selected as analog input |
|||||||||||||||||||||||||||||||||
AnalogInput2 |
2 |
AIN2 selected as analog input |
|||||||||||||||||||||||||||||||||
AnalogInput3 |
3 |
AIN3 selected as analog input |
|||||||||||||||||||||||||||||||||
AnalogInput4 |
4 |
AIN4 selected as analog input |
|||||||||||||||||||||||||||||||||
AnalogInput5 |
5 |
AIN5 selected as analog input |
|||||||||||||||||||||||||||||||||
AnalogInput6 |
6 |
AIN6 selected as analog input |
|||||||||||||||||||||||||||||||||
AnalogInput7 |
7 |
AIN7 selected as analog input |
|||||||||||||||||||||||||||||||||
Address offset: 0x508
Reference source select for single-ended mode
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Id | A | A | A | ||||||||||||||||||||||||||||||||
Reset 0x00000004 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
REFSEL |
Reference select |
||||||||||||||||||||||||||||||||
Int1V2 |
0 |
VREF = internal 1.2 V reference (VDD >= 1.7 V) |
|||||||||||||||||||||||||||||||||
Int1V8 |
1 |
VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V) |
|||||||||||||||||||||||||||||||||
Int2V4 |
2 |
VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V) |
|||||||||||||||||||||||||||||||||
VDD |
4 |
VREF = VDD |
|||||||||||||||||||||||||||||||||
ARef |
7 |
VREF = AREF (VDD >= VREF >= AREFMIN) |
|||||||||||||||||||||||||||||||||
Address offset: 0x50C
External reference select
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Id | A | A | A | ||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
EXTREFSEL |
External analog reference select |
||||||||||||||||||||||||||||||||
AnalogReference0 |
0 |
Use AIN0 as external analog reference |
|||||||||||||||||||||||||||||||||
AnalogReference1 |
1 |
Use AIN1 as external analog reference |
|||||||||||||||||||||||||||||||||
AnalogReference2 |
2 |
Use AIN2 as external analog reference |
|||||||||||||||||||||||||||||||||
AnalogReference3 |
3 |
Use AIN3 as external analog reference |
|||||||||||||||||||||||||||||||||
AnalogReference4 |
4 |
Use AIN4 as external analog reference |
|||||||||||||||||||||||||||||||||
AnalogReference5 |
5 |
Use AIN5 as external analog reference |
|||||||||||||||||||||||||||||||||
AnalogReference6 |
6 |
Use AIN6 as external analog reference |
|||||||||||||||||||||||||||||||||
AnalogReference7 |
7 |
Use AIN7 as external analog reference |
|||||||||||||||||||||||||||||||||
Address offset: 0x530
Threshold configuration for hysteresis unit
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Id | B | B | B | B | B | B | A | A | A | A | A | A | |||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
THDOWN |
[63:0] |
VDOWN = (THDOWN+1)/64*VREF |
|||||||||||||||||||||||||||||||
B | RW |
THUP |
[63:0] |
VUP = (THUP+1)/64*VREF |
|||||||||||||||||||||||||||||||
Address offset: 0x534
Mode configuration
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Id | B | A | A | ||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
SP |
Speed and power modes |
||||||||||||||||||||||||||||||||
Low |
0 |
Low-power mode |
|||||||||||||||||||||||||||||||||
Normal |
1 |
Normal mode |
|||||||||||||||||||||||||||||||||
High |
2 |
High-speed mode |
|||||||||||||||||||||||||||||||||
B | RW |
MAIN |
Main operation modes |
||||||||||||||||||||||||||||||||
SE |
0 |
Single-ended mode |
|||||||||||||||||||||||||||||||||
Diff |
1 |
Differential mode |
|||||||||||||||||||||||||||||||||
Address offset: 0x538
Comparator hysteresis enable
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Id | A | ||||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
HYST |
Comparator hysteresis |
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NoHyst |
0 |
Comparator hysteresis disabled |
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Hyst50mV |
1 |
Comparator hysteresis enabled |
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Address offset: 0x53C
Current source select on analog input
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
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Id |
A |
A |
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Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
ISOURCE |
Comparator hysteresis |
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Off |
0 |
Current source disabled |
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Ien2mA5 |
1 |
Current source enabled (+/- 2.5 uA) |
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Ien5mA |
2 |
Current source enabled (+/- 5 uA) |
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Ien10mA |
3 |
Current source enabled (+/- 10 uA) |
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Symbol | Description | Min. | Typ. | Max. | Units | ||||
---|---|---|---|---|---|---|---|---|---|
ICOMP,LP |
Core run current in low power mode |
2 | µA | ||||||
ICOMP,N |
Core run current in normal mode |
5 | µA | ||||||
ICOMP,HS |
Core run current in high-speed mode |
10 | µA | ||||||
tPROPDLY,LP |
Propagation delay, low-power modea |
0.6 | µS | ||||||
tPROPDLY,N |
Propagation delay, normal modea |
0.2 | µS | ||||||
tPROPDLY,HS |
Propagation delay, high-speed modea |
0.1 | µS | ||||||
VDIFFHYST |
Optional hysteresis applied to differential input |
30 | mV | ||||||
VVDD-VREF |
Required difference between VDD and a selected VREF, VDD > VREF |
0.3 | V | ||||||
IINT_REF |
Current used by the internal bandgap reference when selected as source for VREF |
13 | µA | ||||||
tINT_REF,START |
Startup time for the internal bandgap reference |
50 | 80 | µS | |||||
EINT_REF |
Internal bandgap reference error |
-3 | 3 | % | |||||
RLADDER |
Reference ladder resistance, ILADDER = VREF / RLADDER |
550 | kΩ | ||||||
VINPUTOFFSET |
Input offset |
-10 | 10 | mV | |||||
DNLLADDER |
Differential non-linearity of reference ladder |
<0.1 | LSB | ||||||
tCOMP,START |
Startup time for the comparator core |
3 | µS |
Total comparator run current must be calculated from the ICOMP, IINT_REF, and ILADDER values for a given reference voltage.