COMP — Comparator

The Comparator (COMP) compares the input voltage (VIN+) that is derived from an analog input pin selected via the PSEL register against a second input voltage (VIN-) that can be derived from multiple sources depending on operation mode.

Listed here are the main features for COMP:

Figure 1. Comparator overview

Important: COMP cannot be used (STARTed) at the same time as LPCOMP. Only one comparator can be used at a time.

The COMP is started by triggering the START task, and stopped by triggering the STOP task. After a start-up time of tCOMP,START 1 the COMP will generate a READY event to indicate that the comparator is ready to use and the output of the COMP is correct. When the COMP module is started, events will be generated every time VIN+ crosses VIN-.

VIN- can be derived directly from AIN0 or AIN1 in differential mode, or VREF in single-ended mode. VUP and VDOWN thresholds can be set to implement a hysteresis on VIN- using the Reference Ladder. VREF can be derived from VDD, AIN0, AIN1 or internal 1.2V, 1.8V and 2.4V references.

An upward crossing will generate an UP event and a downward crossing will generate a DOWN event. The CROSS event will be generated every time there is a crossing, independent of direction.

An optional hysteresis on VIN+ and VIN- can be enabled when the module is used in differential mode through the HYST register. In single ended mode the two reference ladders (VUP and VDOWN, see Figure 4) will be used instead of the hysteresis mechanism configured in HYST.

This hysteresis is in the order of magnitude of 50 mV, and shall prevent noise on the signal to create unwanted events. See Figure 5 for illustration of the effect of an active hysteresis on a noisy input signal.

The COMP can be configured to operate in two main operation modes, differential mode and single-ended mode, see MODE register for more information.

The COMP can, for both main operation modes, operate in different speed and power consumption modes, see MODE register. High-speed mode will consume more power compared to low-power mode, and low-power mode will result in slower response time compared to high-speed mode.

The immediate value of the COMP can be sampled to the RESULT register by triggering the SAMPLE task.

A selectable current can be applied (ISOURCE register) on the currently selected AINx line. Enabling the block creates a feedback path around the comparator, forming a relaxation oscillator. The circuit will sink current from VIN+ when the comparator output is high, and source current into VIN+ when the comparator output is low. The frequency of the oscillator is dependent on the capacitance at the analog input pin, the reference voltages and the value of the current source. In this mode, only a capacitive sensor needs to be attached between the analog input pin and ground. With a selected current of 10 μA, VUP-VDOWN equal to 1 V, and an external capacity of typically 10 pF, the resulting oscillation frequency is around 500 kHz.

The frequency of the oscillator can be calculated as
f_OSC = I_SOURCE / (2C∙(VUP-VDOWN) )

Shared resources

The COMP shares analog resources with the SAADC and LPCOMP peripherals.

While it is possible to use SAADC at the same time as COMP or LPCOMP, COMP and LPCOMP are mutually exclusive: enabling one will automatically disable the other. In addition, when using SAADC and COMP or LPCOMP simultaneously, it is not possible to select the same analog input pin for both modules.

Important: The COMP peripheral shall not be disabled (by writing to the ENABLE register) before the peripheral has stopped. Failing to do so may result in unpredictable behaviour.

Differential mode

In differential mode, the reference input VIN- is derived directly from one of the AINx pins.

In this mode, the impedance on VIN-'s signal path is equal to the impedance on VIN+'s signal path. See ZCOMPVINP and ZCOMPVINND for more information. In differential mode, the PSEL, MODE and EXTREFSEL registers must be configured before the COMP is enabled via the ENABLE register. When HYST is turned on while in this mode, the Output of the comparator (and associated events) will change from ABOVE to BELOW whenever VIN+ becomes smaller than (VIN- - (VDIFFHYST / 2) ). Similarly, it will change from BELOW to ABOVE whenever VIN+ becomes larger than (VIN- + (VDIFFHYST / 2) ), as illustrated in Figure 3.

Restriction: Depending on the device, not all the analog inputs may be available for each MUX.
Figure 2. Comparator in differential mode

Figure 3. Hysteresis enabled in differential mode

Single-ended mode

In single-ended mode, VIN- is derived from the Reference Ladder.

The Reference Ladder uses the reference voltage VREF to derive two new voltage references, VUP and VDOWN. VUP and VDOWN are configured via THUP and THDOWN in the TH register. VREF can be sourced from any of the available references sources as illustrated in Figure 4. This is configured via EXTREFSEL and REFSEL.

When the comparator core detects that VIN+ > VIN-, i.e. ABOVE as per the RESULT register, VIN- will switch to VDOWN. When VIN- falls below VIN- again, VIN- will be switched back to VUP. By specifying VUP larger than VDOWN, a hysteresis as illustrated in Figure 5 and Figure 6 can be generated. In single-ended mode, the PSEL, MODE, EXTREFSEL, REFSEL and TH registers must be configured before the COMP is enabled via the ENABLE register.

Restriction: Depending on the device, not all the analog inputs may be available for each MUX.

Writing to the HYST register has no effect in single-ended mode, and the content of this register is ignored.

Figure 4. Comparator in single-ended mode

Figure 5. Hysteresis example where VIN+ starts below VUP

Figure 6. Hysteresis example where VIN+ starts above VUP

Pin configuration

The user can use the PSEL register to select one of the analog input pins, AIN0 through AIN7, as input VIN+.

See Figure 4. Similarly the user can use the EXTREFSEL register to select one of the AINx analog input pins as reference input, in case AREF is selected in REFSEL. The selected analog pins will be acquired by the COMP when it is enabled via the ENABLE register.

Depending on the device, not all the analog inputs may be available for each MUX. See PSEL and EXTREFSEL register definition for more information about which analog pins are available on a particular device.

Registers

Table 1. Instances
Base address Peripheral Instance Description Configuration
0x40013000 COMP COMP

General purpose comparator

   
Table 2. Register Overview
Register Offset Description
TASKS_START 0x000

Start comparator

 
TASKS_STOP 0x004

Stop comparator

 
TASKS_SAMPLE 0x008

Sample comparator value

 
EVENTS_READY 0x100

COMP is ready and output is valid

 
EVENTS_DOWN 0x104

Downward crossing

 
EVENTS_UP 0x108

Upward crossing

 
EVENTS_CROSS 0x10C

Downward or upward crossing

 
SHORTS 0x200

Shortcut register

 
INTEN 0x300

Enable or disable interrupt

 
INTENSET 0x304

Enable interrupt

 
INTENCLR 0x308

Disable interrupt

 
RESULT 0x400

Compare result

 
ENABLE 0x500

COMP enable

 
PSEL 0x504

Pin select

 
REFSEL 0x508

Reference source select

 
EXTREFSEL 0x50C

External reference select

 
TH 0x530

Threshold configuration for hysteresis unit

 
MODE 0x534

Mode configuration

 
HYST 0x538

Comparator hysteresis enable

 
ISOURCE 0x53C

Current source select on analog input

 

SHORTS

Address offset: 0x200

Shortcut register

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                       E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

READY_SAMPLE

   

Shortcut between READY event and SAMPLE task

See EVENTS_READY and TASKS_SAMPLE

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

B RW

READY_STOP

   

Shortcut between READY event and STOP task

See EVENTS_READY and TASKS_STOP

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

C RW

DOWN_STOP

   

Shortcut between DOWN event and STOP task

See EVENTS_DOWN and TASKS_STOP

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

D RW

UP_STOP

   

Shortcut between UP event and STOP task

See EVENTS_UP and TASKS_STOP

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

E RW

CROSS_STOP

   

Shortcut between CROSS event and STOP task

See EVENTS_CROSS and TASKS_STOP

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

 

INTEN

Address offset: 0x300

Enable or disable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                         D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

READY

   

Enable or disable interrupt for READY event

See EVENTS_READY

     

Disabled

0

Disable

     

Enabled

1

Enable

B RW

DOWN

   

Enable or disable interrupt for DOWN event

See EVENTS_DOWN

     

Disabled

0

Disable

     

Enabled

1

Enable

C RW

UP

   

Enable or disable interrupt for UP event

See EVENTS_UP

     

Disabled

0

Disable

     

Enabled

1

Enable

D RW

CROSS

   

Enable or disable interrupt for CROSS event

See EVENTS_CROSS

     

Disabled

0

Disable

     

Enabled

1

Enable

 

INTENSET

Address offset: 0x304

Enable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                         D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

READY

   

Write '1' to Enable interrupt for READY event

See EVENTS_READY

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

B RW

DOWN

   

Write '1' to Enable interrupt for DOWN event

See EVENTS_DOWN

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

C RW

UP

   

Write '1' to Enable interrupt for UP event

See EVENTS_UP

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

D RW

CROSS

   

Write '1' to Enable interrupt for CROSS event

See EVENTS_CROSS

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

 

INTENCLR

Address offset: 0x308

Disable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                         D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

READY

   

Write '1' to Disable interrupt for READY event

See EVENTS_READY

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

B RW

DOWN

   

Write '1' to Disable interrupt for DOWN event

See EVENTS_DOWN

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

C RW

UP

   

Write '1' to Disable interrupt for UP event

See EVENTS_UP

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

D RW

CROSS

   

Write '1' to Disable interrupt for CROSS event

See EVENTS_CROSS

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

 

RESULT

Address offset: 0x400

Compare result

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A R

RESULT

   

Result of last compare. Decision point SAMPLE task.

     

Below

0

Input voltage is below the threshold (VIN+ < VIN-)

     

Above

1

Input voltage is above the threshold (VIN+ > VIN-)

 

ENABLE

Address offset: 0x500

COMP enable

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                             A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

ENABLE

   

Enable or disable COMP

     

Disabled

0

Disable

     

Enabled

2

Enable

 

PSEL

Address offset: 0x504

Pin select

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                           A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

PSEL

   

Analog pin select

     

AnalogInput0

0

AIN0 selected as analog input

     

AnalogInput1

1

AIN1 selected as analog input

     

AnalogInput2

2

AIN2 selected as analog input

     

AnalogInput3

3

AIN3 selected as analog input

     

AnalogInput4

4

AIN4 selected as analog input

     

AnalogInput5

5

AIN5 selected as analog input

     

AnalogInput6

6

AIN6 selected as analog input

     

AnalogInput7

7

AIN7 selected as analog input

 

REFSEL

Address offset: 0x508

Reference source select

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                           A A A
Reset 0x00000004 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
Id RW Field Value Id Value Description
A RW

REFSEL

   

Reference select

     

Int1V2

0

VREF = internal 1.2 V reference (VDD >= 1.7 V)

     

Int1V8

1

VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V)

     

Int2V4

2

VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V)

     

VDD

4

VREF = VDD

     

ARef

7

VREF = AREF (VDD >= VREF >= AREFMIN)

 

EXTREFSEL

Address offset: 0x50C

External reference select

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                           A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

EXTREFSEL

   

External analog reference select

     

AnalogReference0

0

Use AIN0 as external analog reference

     

AnalogReference1

1

Use AIN1 as external analog reference

 

TH

Address offset: 0x530

Threshold configuration for hysteresis unit

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                     B B B B B B     A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

THDOWN

 

[63:0]

VDOWN = (THDOWN+1)/64*VREF

B RW

THUP

 

[63:0]

VUP = (THUP+1)/64*VREF

 

MODE

Address offset: 0x534

Mode configuration

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                               B             A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

SP

   

Speed and power mode

     

Low

0

Low power mode

     

Normal

1

Normal mode

     

High

2

High speed mode

B RW

MAIN

   

Main operation mode

     

SE

0

Single ended mode

     

Diff

1

Differential mode

 

HYST

Address offset: 0x538

Comparator hysteresis enable

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

HYST

   

Comparator hysteresis

     

NoHyst

0

Comparator hysteresis disabled

     

Hyst50mV

1

Comparator hysteresis enabled

 

ISOURCE

Address offset: 0x53C

Current source select on analog input

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                             A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

ISOURCE

   

Comparator hysteresis

     

Off

0

Current source disabled

     

Ien2mA5

1

Current source enabled (+/- 2.5 uA)

     

Ien5mA

2

Current source enabled (+/- 5 uA)

     

Ien10mA

3

Current source enabled (+/- 10 uA)

 

Electrical specification

COMP Electrical Specification

Symbol Description Min. Typ. Max. Units
ICOMP,LP

Core run current in low power mode

2 µA
ICOMP,N

Core run current in normal mode

5 µA
ICOMP,HS

Core run current in high-speed mode

10 µA
tPROPDLY,LP

Propagation delay, low power modea

0.6 µS
tPROPDLY,N

Propagation delay, normal modea

0.2 µS
tPROPDLY,HS

Propagation delay, high-speed modea

0.1 µS
ISOURCE

Configurable input current provided by the output driven current source.

µA
ISOURCE,A

2.5 µA
ISOURCE,B

5.0 µA
ISOURCE,C

10.0 µA
VDIFFHYST

Optional hysteresis applied to differential input

30 mV
VVDD-VREF

Required difference between VDD and a selected VREF, VDD > VREF

0.3 V
IINT_REF

Current used by the internal bandgap reference when selected as source for VREF

13 µA
tINT_REF,START

Startup time for the internal bandgap reference

50 80 µS
EINT_REF

Internal bandgap reference error

-3 3 %
RLADDER

Reference ladder resistance, ILADDER = VREF / RLADDER

550 kΩ
VINPUTOFFSET

Input offset

-10 10 mV
DNLLADDER

Differential non-linearity of reference ladder

<0.1 LSB
tCOMP,START

Startup time for the comparator core

3 µS

Total comparator run current must be calculated from the ICOMP, IINT_REF, ISOURCE and ILADDER values for a given reference voltage.

1 See tPROPDLY,LP, tPROPDLY,N, tPROPDLY,HS, ICOMP,LP, ICOMP,N and ICOMP,HS in Electrical parameters for more information about COMP speed and power characteristics related to these different modes.
a Propagation delay is with 10mV overdrive.

Documentation feedback | Developer Zone | Updated 2017-02-09