Test points

Table 1. Pinout of connector P3
Test point Location Signal Description
TP1 Bottom N.A. Reserved
TP2 Bottom RF_SW1 Bit 0 of RF switch control signals
TP3 Bottom RF_SW2 Bit 1 of RF switch control signals
TP4 Bottom RF_SW3 Bit 2 of RF switch control signals
TP5 Bottom N.A. Reserved
TP6 Bottom N.A. Reserved
TP7 Bottom nRF91-P0.10 General-Purpose Input/Output (GPIO) of the nRF9160
TP8 Top nRF52-P0.18/RESET GPIO/RESET of the nRF52840
TP9 Top SCL I2C clock line
TP10 Top SDA I2C data line
TP11 Top VBUS' USB voltage before power switch
TP12 Top VBUS USB voltage after power switch
TP13 Top VLi-Ion' Battery voltage before power switch
TP14 Top VLi-Ion Battery voltage after power switch
TP15 Top GND Ground
TP16 Top GND Ground
TP17 Top VSYS Internal power domain of PMIC and default nRF9160 power supply
TP18 Top 1V8 Regulated 1.8 V domain
TP19 Top 3V3 Regulated 3.3 V domain
TP20 Bottom ADP_PGOOD1 PMIC output status indication pin 1
TP21 Bottom ADP_PGOOD2 PMIC output status indication pin 2
TP22 Bottom ADP_STP Stop the buck regulator switching of PMIC
TP23 Bottom ADP_RESET PMIC reset output
TP24 Bottom ADP_MR PMIC manual reset input
TP25 Bottom SPARE7 GPIO of the nRF52840
TP26 Bottom SPARE8 GPIO of the nRF52840
TP27 Top SWDIO Programming interface data line
TP28 Top SWDSEL Programming interface target select
TP29 Top SWDCLK Programming interface clock line
TP30 Top D- USB data line
TP31 Top D+ USB data line
TP32 Top nRF91-P0.13/AIN0 Analog/digital GPIO of the nRF9160, combined with N-MOS1
TP33 Top nRF91-P0.16/AIN3 Analog/digital GPIO of the nRF9160, combined with N-MOS4
TP34 Top SCK SPI clock line
TP35 Top MOSI SPI master output, slave input data line
TP36 Top MISO SPI master input, slave output data line
TP37 Top ADXL372_CS High-G accelerometer chip select line
TP38 Top ADXL362_CS Low-power accelerometer chip select line