nRF7002 DK v1.0.0

Debug input and trace

The Debug in connector (P18) makes it possible to connect external debuggers for debugging when the interface MCU USB cable is not connected or the Development Kit (DK) is in interface MCU disable mode.

For trace, a footprint for a 20-pin connector is available (P25). If trace functionality is required, it is possible to mount a 2x10 pin 1.27 mm pitch surface-mount pin header.

Figure 1. Debug input and trace connectors
Debug input connector (P18) and trace connector (P25) on nRF7002 DK

Figure 2. The trace pins out of the nRF5340 on the back of the DK
nRF7002 DK: SB11-SB14 are the trace pins out of the nRF5340 on the back of the DK

Table 1. Default and Trace GPIOs
GPIO Trace Default use
P0.12 TRACECLK nRF5340 Buck Enable. SB7 disconnects Buck Enable. Short SB9 to use alternative signal for BUCK_EN.
P0.11 TRACEDATA[0] External memory, default disconnected
P0.10 TRACEDATA[1] External memory, default disconnected
P0.09 TRACEDATA[2] External memory, default disconnected
P0.08 TRACEDATA[3] External memory, default disconnected
Figure 3. nRF7002 DK debug and trace headers
nRF7002 DK debug and trace headers

The reference voltage for the debug input and trace is by default connected to VDD. This can be connected to VDD_MEAS by cutting SB59 and soldering SB60.