The nRF5340 DK has a 64 Mb external flash memory. The memory is a multi-I/O memory supporting both regular Serial Peripheral Interface (SPI) and Quad SPI (QSPI).
Note: Running the QSPI at 96 MHz requires 1.8 V board voltage because a higher board voltage might cause RF interference. You can change the board voltage by supplying 1.8 V to the VIO_REF pin on P20. See the nRF5340 Errata for more information.
The memory is connected to the chip using the following General-Purpose Input/Output (GPIO)s:
| GPIO | Flash memory pin | Solder bridge for memory use (default: shorted) | Solder bridge for GPIO use (default: open) |
|---|---|---|---|
| P0.18 | CS | SB13 | SB23 |
| P0.17 | SCLK | SB11 | SB21 |
| P0.13 | SIO_0/SI | SB12 | SB22 |
| P0.14 | SIO_1/SO | SB14 | SB24 |
| P0.15 | SIO_2/WP | SB15 | SB25 |
| P0.16 | SIO_3/HOLD | SB10 | SB20 |
To use the GPIOs for a purpose other than the onboard external memory and have them available
on the P24 connector, six solder bridges (SB10–SB15) must be cut
and six solder bridges (SB20–SB25) must be shorted. See the following
figure for details.
Note: If debugging the QSPI communication is needed, the
SB20–SB25 can be shorted without cutting SB10–SB15,
but the pins should not be driven externally.
Figure 1. Configuring GPIOs for external memory
By default, the power supply of the external memory is coming from the VDD domain and it is controlled by the nRF only switch (SW6). In the nRF only mode, there are two optional power sources for keeping the external memory powered, VDD and VDD_nRF. If VDD_nRF is selected, the power consumption of the external memory is added to the nRF5340 current measured on P22 or P23. See the following table for configuration.
| Power source | Solder bridge | Default state |
|---|---|---|
| VDD_PER | SB16 | Shorted |
| VDD | SB17 | Open |
| VDD_nRF | SB18 | Open |