UICR — User information configuration registers

The user information configuration registers (UICRs) are non-volatile memory (NVM) registers for configuring user specific settings.

For information on writing UICR registers, see the NVMC — Non-volatile memory controller and Memory chapters.

Registers

Instances

Instance Base address TrustZone Split access Description
Map Att DMA
UICR 0x00FF8000 HF S NA No

User information configuration

Register overview

Register Offset TZ Description
APPROTECT 0x000  

Access port protection

XOSC32M 0x014  

Oscillator control

HFXOSRC 0x01C  

HFXO clock source selection

HFXOCNT 0x020  

HFXO startup counter

APPNVMCPOFGUARD 0x024  

Enable blocking NVM WRITE and aborting NVM ERASE for Application NVM in POFWARN condition.

SECUREAPPROTECT 0x02C  

Secure access port protection

ERASEPROTECT 0x030  

Erase protection

OTP[n] 0x108  

One time programmable memory

KEYSLOT.CONFIG[n].DEST 0x400  

Destination address where content of the key value registers (KEYSLOT.KEYn.VALUE[0-3]) will be pushed by KMU. Note that this address must match that of a peripheral's APB mapped write-only key registers, otherwise the KMU can push this key value into an address range which the CPU can potentially read.

KEYSLOT.CONFIG[n].PERM 0x404  

Define permissions for the key slot. Bits 0-15 and 16-31 can only be written when equal to 0xFFFF.

KEYSLOT.KEY[n].VALUE[o] 0x800  

Define bits [31+o*32:0+o*32] of value assigned to KMU key slot.

APPROTECT

Address offset: 0x000

Access port protection

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID R/W Field Value ID Value Description
A

RW

PALL

 

Blocks debugger read/write access to all CPU registers and memory mapped addresses

Any value different to HwUnprotected will make access port protected.

     

HwUnprotected

0x50FA50FA

HwUnprotected

     

Protected

0x00000000

Protected

XOSC32M

Address offset: 0x014

Oscillator control

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                     A A A A A A
Reset 0xFFFFFFCF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1
ID R/W Field Value ID Value Description
A

RW

CTRL

 

Pierce current DAC control signals

HFXOSRC

Address offset: 0x01C

HFXO clock source selection

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID R/W Field Value ID Value Description
A

RW

HFXOSRC

 

HFXO clock source selection

     

XTAL

1

32 MHz crystal oscillator

     

TCXO

0

32 MHz temperature compensated crystal oscillator (TCXO)

HFXOCNT

Address offset: 0x020

HFXO startup counter

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                 A A A A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID R/W Field Value ID Value Description
A

RW

HFXOCNT

 

HFXO startup counter. Total debounce time = HFXOCNT*64 us + 0.5 us

     

MinDebounceTime

0

Min debounce time = (0*64 us + 0.5 us)

     

MaxDebounceTime

255

Max debounce time = (255*64 us + 0.5 us)

APPNVMCPOFGUARD

Address offset: 0x024

Enable blocking NVM WRITE and aborting NVM ERASE for Application NVM in POFWARN condition.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID R/W Field Value ID Value Description
A

RW

NVMCPOFGUARDEN

 

Enable blocking NVM WRITE and aborting NVM ERASE in POFWARN condition

     

Disabled

0

NVM WRITE and NVM ERASE are not blocked in POFWARN condition

     

Enabled

1

NVM WRITE and NVM ERASE are blocked in POFWARN condition

SECUREAPPROTECT

Address offset: 0x02C

Secure access port protection

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID R/W Field Value ID Value Description
A

RW

PALL

 

Blocks debugger read/write access to all secure CPU registers and secure memory mapped addresses

Any value different to HwUnprotected will make access port protected.

     

HwUnprotected

0x50FA50FA

HwUnprotected

     

Protected

0x00000000

Protected

ERASEPROTECT

Address offset: 0x030

Erase protection

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID R/W Field Value ID Value Description
A

RW

PALL

 

Blocks NVMC ERASEALL and CTRLAP ERASEALL functionality

     

Unprotected

0xFFFFFFFF

Unprotected

     

Protected

0x00000000

Protected

OTP[n] (n=0..189)

Address offset: 0x108 + (n × 0x4)

One time programmable memory

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B B B B B B B B B B B B B B B B A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID R/W Field Value ID Value Description
A

RW1

LOWER

 

Lower half word

Note: Can only be written to a non 0xFFFF value once.
B

RW1

UPPER

 

Upper half word

Note: Can only be written to a non 0xFFFF value once.

KEYSLOT.CONFIG[n].DEST (n=0..127)

Address offset: 0x400 + (n × 0x8)

Destination address where content of the key value registers (KEYSLOT.KEYn.VALUE[0-3]) will be pushed by KMU. Note that this address must match that of a peripheral's APB mapped write-only key registers, otherwise the KMU can push this key value into an address range which the CPU can potentially read.

Note: Writing/reading this register requires the KMU SELECTKEYSLOT register to be set to n+1.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID R/W Field Value ID Value Description
A

RW

DEST

 

Secure APB destination address

KEYSLOT.CONFIG[n].PERM (n=0..127)

Address offset: 0x404 + (n × 0x8)

Define permissions for the key slot. Bits 0-15 and 16-31 can only be written when equal to 0xFFFF.

Note: Writing/reading this register requires the KMU SELECTKEYSLOT register to be set to n+1.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                               D                           C B A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID R/W Field Value ID Value Description
A

RW

WRITE

 

Write permission for key slot

     

Disabled

0

Disable write to the key value registers

     

Enabled

1

Enable write to the key value registers

B

RW

READ

 

Read permission for key slot

     

Disabled

0

Disable read from key value registers

     

Enabled

1

Enable read from key value registers

C

RW

PUSH

 

Push permission for key slot

     

Disabled

0

Disable pushing of key value registers over secure APB, but can be read if field READ is Enabled

     

Enabled

1

Enable pushing of key value registers over secure APB. Register KEYSLOT.CONFIGn.DEST must contain a valid destination address!

D

RW

STATE

 

Revocation state for the key slot

Note that it is not possible to undo a key revocation by writing the value '1' to this field

     

Revoked

0

Key value registers can no longer be read or pushed

     

Active

1

Key value registers are readable (if enabled) and can be pushed (if enabled)

KEYSLOT.KEY[n].VALUE[o] (n=0..127) (o=0..3)

Address offset: 0x800 + (n × 0x10) + (o × 0x4)

Define bits [31+o*32:0+o*32] of value assigned to KMU key slot.

Note: Writing/reading this register requires the KMU SELECTKEYSLOT register to be set to n+1.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID R/W Field Value ID Value Description
A

RW

VALUE

 

Define bits [31+o*32:0+o*32] of value assigned to KMU key slot