TPIU — Trace port interface unit

The ARM® CoreSight™ TPIU connects an ATB to an external trace port.

This document only provides a register-level description of this ARM component. See the ARM® CoreSight™ SoC-400 Technical Reference Manual for more details

Registers

Instances

Instance	Base address	TrustZone			Split access	Description
Instance	Base address	Map	Att	DMA	Split access	Description
TPIU	0xE0054000	HF	NS	NA	No	TPIU

Register overview

Register	Offset	Description
SUPPORTEDPORTSIZES	0x000	Each bit location is a single port size that is supported on the device.
CURRENTPORTSIZE	0x004	Each bit location is a single port size. One bit can be set, and indicates the current port size.
SUPPORTEDTRIGGERMODES	0x100	The Supported_trigger_modes register indicates the implemented trigger counter multipliers and other supported features of the trigger system.
TRIGGERCOUNTERVALUE	0x104	The Trigger_counter_value register enables delaying the indication of triggers to any external connected trace capture or storage devices.
TRIGGERMULTIPLIER	0x108	The Trigger_multiplier register contains the selectors for the trigger counter multiplier.
SUPPPORTEDTESTPATTERNMODES	0x200	The Supported_test_pattern_modes register provides a set of known bit sequences or patterns that can be output over the trace port and can be detected by the TPA or other associated trace capture device.
CURRENTTESTPATTERNMODES	0x204	Current_test_pattern_mode indicates the current test pattern or mode selected.
TPRCR	0x208	The TPRCR register is an 8-bit counter start value that is decremented. A write sets the initial counter value and a read returns the programmed value.
FFSR	0x300	The FFSR register indicates the current status of the formatter and flush features available in the TPIU.
FFCR	0x304	The FFCR register controls the generation of stop, trigger, and flush events.
FSCR	0x308	The FSCR register enables the frequency of synchronization information to be optimized to suit the Trace Port Analyzer (TPA) capture buffer size.
EXTCTLINPORT	0x400	Two ports can be used as a control and feedback mechanism for any serializers, pin sharing multiplexers, or other solutions that might be added to the trace output pins either for pin control or a high-speed trace port solution.
EXTCTLOUTPORT	0x404	Two ports can be used as a control and feedback mechanism for any serializers, pin sharing multiplexers, or other solutions that might be added to the trace output pins either for pin control or a high speed trace port solution. These ports are raw register banks that sample or export the corresponding external pins.
ITTRFLINACK	0xEE4	The ITTRFLINACK register enables control of the triginack and flushinack outputs from the TPIU.
ITTRFLIN	0xEE8	The ITTRFLIN register contains the values of the flushin and trigin inputs to the TPIU.
ITATBDATA0	0xEEC	The ITATBDATA0 register contains the value of the atdatas inputs to the TPIU. The values are valid only when atvalids is HIGH.
ITATBCTR2	0xEF0	Enables control of the atreadys and afvalids outputs of the TPIU.
ITATBCTR1	0xEF4	The ITATBCTR1 register contains the value of the atids input to the TPIU. This is only valid when atvalids is HIGH.
ITATBCTR0	0xEF8	The ITATBCTR0 register captures the values of the atvalids, afreadys, and atbytess inputs to the TPIU. To ensure the integration registers work correctly in a system, the value of atbytess is only valid when atvalids, bit[0], is HIGH.
ITCTRL	0xF00	Used to enable topology detection. This register enables the component to switch from a functional mode, the default behavior, to integration mode where the inputs and outputs of the component can be directly controlled for integration testing and topology solving.
CLAIMSET	0xFA0	Software can use the claim tag to coordinate application and debugger access to trace unit functionality. The claim tags have no effect on the operation of the component. The CLAIMSET register sets bits in the claim tag, and determines the number of claim bits implemented.
CLAIMCLR	0xFA4	Software can use the claim tag to coordinate application and debugger access to trace unit functionality. The claim tags have no effect on the operation of the component. The CLAIMCLR register sets the bits in the claim tag to 0 and determines the current value of the claim tag.
LAR	0xFB0	This is used to enable write access to device registers.
LSR	0xFB4	This indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug. Accesses to the extended stimulus port registers are not affected by the lock mechanism. This register must always be present although there might not be any lock access control mechanism. The lock mechanism, where present and locked, must block write accesses to any control register, except the Lock Access Register. For most components this covers all registers except for the Lock Access Register.
AUTHSTATUS	0xFB8	Indicates the current level of tracing permitted by the system
DEVID	0xFC8	Indicates the capabilities of the component.
DEVTYPE	0xFCC	The DEVTYPE register provides a debugger with information about the component when the Part Number field is not recognized. The debugger can then report this information.
PIDR4	0xFD0	Coresight peripheral identification registers.
PIDR[0]	0xFE0	Coresight peripheral identification registers.
PIDR[1]	0xFE4	Coresight peripheral identification registers.
PIDR[2]	0xFE8	Coresight peripheral identification registers.
PIDR[3]	0xFEC	Coresight peripheral identification registers.
CIDR[0]	0xFF0	Coresight component identification registers.
CIDR[1]	0xFF4	Coresight component identification registers.
CIDR[2]	0xFF8	Coresight component identification registers.
CIDR[3]	0xFFC	Coresight component identification registers.

SUPPORTEDPORTSIZES

Address offset: 0x000

Each bit location is a single port size that is supported on the device.

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				f	e	d	c	b	a	Z	Y	X	W	V	U	T	S	R	Q	P	O	N	M	L	K	J	I	H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A-f	RW	PORT_SIZE_[i+1] (i=0..31)										Indicates whether the TPIU supports port size of i+1-bit.
			NotSupported	0								Port size i+1 is not supported.
			Supported	1								Port size i+1 is supported.

CURRENTPORTSIZE

Address offset: 0x004

Each bit location is a single port size. One bit can be set, and indicates the current port size.

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				f	e	d	c	b	a	Z	Y	X	W	V	U	T	S	R	Q	P	O	N	M	L	K	J	I	H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A-f	RW	PORT_SIZE_[i+1] (i=0..31)										Indicates which port size is currently selected.
			NotSelected	0								Port size i+1 is not selected.
			Selected	1								Port size i+1 is selected.

SUPPORTEDTRIGGERMODES

Address offset: 0x100

The Supported_trigger_modes register indicates the implemented trigger counter multipliers and other supported features of the trigger system.

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																		H	G								F				E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A-E	RW	MULT[i] (i=0..4)										Indicates whether multiplying the trigger counter by 2^(i+1) is supported.
			NotSelected	0								Multiplying the trigger counter by 2^(i+1) is supported.
			Selected	1								Multiplying the trigger counter by 2^(i+1) is supported.
F	RW	TCOUNT8										Indicates whether an 8-bit wide counter register is implemented.
			NotImplemented	0								An 8-bit wide counter register is implemented.
			Implemented	1								An 8-bit wide counter register is implemented.
G	RW	TRIGGERED										A trigger has occurred and the counter has reached 0.
			NotOccured	0								Trigger has not occurred.
			Occured	1								Trigger has occurred.
H	RW	TRGRUN										A trigger has occurred but the counter is not at 0.
			NotOccured	0								Either a trigger has not occurred or the counter is at 0.
			Occured	1								A trigger has occurred but the counter is not at 0.

TRIGGERCOUNTERVALUE

Address offset: 0x104

The Trigger_counter_value register enables delaying the indication of triggers to any external connected trace capture or storage devices.

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																												A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TrigCount		[0:255]								8-bit counter value for the number of words to be output from the formatter before a trigger is inserted.

TRIGGERMULTIPLIER

Address offset: 0x108

The Trigger_multiplier register contains the selectors for the trigger counter multiplier.

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																															E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A-E	RW	MULT[i] (i=0..4)										Multiply the Trigger Counter by 2^n.
			Disabled	0								Multiplier disabled.
			Enabled	1								Multiplier enabled.

SUPPPORTEDTESTPATTERNMODES

Address offset: 0x200

The Supported_test_pattern_modes register provides a set of known bit sequences or patterns that can be output over the trace port and can be detected by the TPA or other associated trace capture device.

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																		F	E													D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	PATW1										Indicates whether the walking 1s pattern is supported as output over the trace port.
			NotSupported	0								Test pattern is not supported.
			Supported	1								Test pattern is supported.
B	RW	PATW0										Indicates whether the walking 0s pattern is supported as output over the trace port.
			NotSupported	0								Test pattern is not supported.
			Supported	1								Test pattern is supported.
C	RW	PATA5										Indicates whether the AA/55 pattern is supported as output over the trace port.
			NotSupported	0								Test pattern is not supported.
			Supported	1								Test pattern is supported.
D	RW	PATF0										Indicates whether the FF/00 pattern is supported as output over the trace port.
			NotSupported	0								Test pattern is not supported.
			Supported	1								Test pattern is supported.
E	RW	PTIMEEN										Indicates whether timed mode is supported.
			NotSupported	0								Mode is not supported.
			Supported	1								Mode is supported.
F	RW	PCONTEN										Indicates whether continuous mode is supported.
			NotSupported	0								Mode is not supported.
			Supported	1								Mode is supported.

CURRENTTESTPATTERNMODES

Address offset: 0x204

Current_test_pattern_mode indicates the current test pattern or mode selected.

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																		F	E													D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	PATW1										Indicates whether the walking 1s pattern is supported as output over the trace port.
			Disabled	0								Test pattern is disabled.
			Enabled	1								Test pattern is enabled.
B	RW	PATW0										Indicates whether the walking 0s pattern is supported as output over the trace port.
			Disabled	0								Test pattern is disabled.
			Enabled	1								Test pattern is enabled.
C	RW	PATA5										Indicates whether the AA/55 pattern is supported as output over the trace port.
			Disabled	0								Test pattern is disabled.
			Enabled	1								Test pattern is enabled.
D	RW	PATF0										Indicates whether the FF/00 pattern is supported as output over the trace port.
			Disabled	0								Test pattern is disabled.
			Enabled	1								Test pattern is enabled.
E	RW	PTIMEEN										Indicates whether timed mode is supported.
			Disabled	0								Mode is disabled.
			Enabled	1								Mode is enabled.
F	RW	PCONTEN										Indicates whether continuous mode is supported.
			Disabled	0								Mode is disabled.
			Enabled	1								Mode is enabled.

TPRCR

Address offset: 0x208

The TPRCR register is an 8-bit counter start value that is decremented. A write sets the initial counter value and a read returns the programmed value.

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																												A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	PATTCOUNT		[0:255]								8-bit counter value to indicate the number of traceclkin cycles for which a pattern runs before it switches to the next pattern.

FFSR

Address offset: 0x300

The FFSR register indicates the current status of the formatter and flush features available in the TPIU.

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	FLINPROG										Flush in progress.
			NotInProgress	0								A flush is not in progress.
			InProgress	1								A flush is in progress.
B	RW	FTSTOPPED										The formatter has received a stop request signal and all trace data and post-amble is sent. Any additional trace data on the ATB interface is ignored and atreadys goes HIGH.
			Running	0								Formatter has not stopped.
			Stopped	1								Formatter has stopped.
C	RW	TCPRESENT										Indicates whether the TRACECTL pin is available for use.
			NotPresent	0								TRACECTL pin is not present.
			Present	1								TRACECTL pin is present.

FFCR

Address offset: 0x304

The FFCR register controls the generation of stop, trigger, and flush events.

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																						K	J		I	H	G	F	E	D	C			B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	ENFTC										Do not embed triggers into the formatted stream. Trace disable cycles and triggers are indicated by tracectl, where present.
			Disabled	0								The formatting feature is disabled.
			Enabled	1								The formatting feature is enabled.
B	RW	ENFCONT										Is embedded in trigger packets and indicates that no cycle is using sync packets.
			Disabled	0								The formatting feature is disabled.
			Enabled	1								The formatting feature is enabled.
C	RW	FONFLIN										Enables the use of the flushin connection.
			Disabled	0								The formatting feature is disabled.
			Enabled	1								The formatting feature is enabled.
D	RW	FONTRIG										Initiates a manual flush of data in the system when a trigger event occurs.
			Disabled	0								The formatting feature is disabled.
			Enabled	1								The formatting feature is enabled.
E	RW	FONMANR										Generates a flush. This bit is set to 0 when this flush is serviced.
			Disabled	0								The formatting feature is disabled.
			Enabled	1								The formatting feature is enabled.
F	RW	FONMANW										Generates a flush. This bit is set to 1 when this flush is serviced.
			Disabled	0								The formatting feature is disabled.
			Enabled	1								The formatting feature is enabled.
G	RW	TRIGIN										Indicates a trigger when trigin is asserted.
			Disabled	0								The formatting feature is disabled.
			Enabled	1								The formatting feature is enabled.
H	RW	TRIGEVT										Indicates a trigger on a trigger event.
			Disabled	0								The formatting feature is disabled.
			Enabled	1								The formatting feature is enabled.
I	RW	TRIGFL										Indicates a trigger when flush completion on afreadys is returned.
			Disabled	0								The formatting feature is disabled.
			Enabled	1								The formatting feature is enabled.
J	RW	STOPFL										Forces the FIFO to drain off any part-completed packets.
			Disabled	0								The formatting feature is disabled.
			Enabled	1								The formatting feature is enabled.
K	RW	STOPTRIG										Stops the formatter after a trigger event is observed. Reset to disabled or 0.
			Disabled	0								The formatting feature is disabled.
			Enabled	1								The formatting feature is enabled.

FSCR

Address offset: 0x308

The FSCR register enables the frequency of synchronization information to be optimized to suit the Trace Port Analyzer (TPA) capture buffer size.

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																								A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CYCCOUNT		[0:1024]								12-bit counter reload value. Indicates the number of complete frames between full synchronization packets.

EXTCTLINPORT

Address offset: 0x400

Two ports can be used as a control and feedback mechanism for any serializers, pin sharing multiplexers, or other solutions that might be added to the trace output pins either for pin control or a high-speed trace port solution.

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																												H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A-H	RW	EXTCTLIN[i] (i=0..7)										EXTCTL inputs.
			Low	0								Input EXTCTLi is low.
			High	1								Input EXTCTLi is high.

EXTCTLOUTPORT

Address offset: 0x404

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																												H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A-H	RW	EXTCTLOUT[i] (i=0..7)										EXTCTL outputs.
			Low	0								Output EXTCTLi is low.
			High	1								Output EXTCTLi is high.

ITTRFLINACK

Address offset: 0xEE4

The ITTRFLINACK register enables control of the triginack and flushinack outputs from the TPIU.

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																		B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TRIGINACK										Sets the value of triginack.
			Low	0								Pin is logic 0.
			High	1								Pin is logic 1.
B	RW	FLUSHINACK										Sets the value of flushinack.
			Low	0								Pin is logic 0.
			High	1								Pin is logic 1.

ITTRFLIN

Address offset: 0xEE8

The ITTRFLIN register contains the values of the flushin and trigin inputs to the TPIU.

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																		B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	TRIGIN										Reads the value of trigin.
			Low	0								Pin is logic 0.
			High	1								Pin is logic 1.
B	RW	FLUSHIN										Reads the value of flushin.
			Low	0								Pin is logic 0.
			High	1								Pin is logic 1.

ITATBDATA0

Address offset: 0xEEC

The ITATBDATA0 register contains the value of the atdatas inputs to the TPIU. The values are valid only when atvalids is HIGH.

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																															E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A-E	RW	ATDATA[i] (i=0..4)										A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port.
			Low	0								Pin is logic 0.
			High	1								Pin is logic 1.

ITATBCTR2

Address offset: 0xEF0

Enables control of the atreadys and afvalids outputs of the TPIU.

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																		B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	ATREADY										Sets the value of afvalid.
			Low	0								Pin is logic 0.
			High	1								Pin is logic 1.
B	RW	AFVALID										Sets the value of atready.
			Low	0								Pin is logic 0.
			High	1								Pin is logic 1.

ITATBCTR1

Address offset: 0xEF4

The ITATBCTR1 register contains the value of the atids input to the TPIU. This is only valid when atvalids is HIGH.

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																													A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	ATID										Reads the value of atids.
			Low	0								Pin is logic 0.
			High	1								Pin is logic 1.

ITATBCTR0

Address offset: 0xEF8

The ITATBCTR0 register captures the values of the atvalids, afreadys, and atbytess inputs to the TPIU. To ensure the integration registers work correctly in a system, the value of atbytess is only valid when atvalids, bit[0], is HIGH.

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																										C	C						B		A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	ATVALID										Reads the value of atvalids.
			Low	0								Pin is logic 0.
			High	1								Pin is logic 1.
B	RW	AFREADY										Reads the value of afreadys.
			Low	0								Pin is logic 0.
			High	1								Pin is logic 1.
C	RW	ATBYTES										Reads the value of atbytess.
			Low	0								Pin is logic 0.
			High	1								Pin is logic 1.

ITCTRL

Address offset: 0xF00

Used to enable topology detection. This register enables the component to switch from a functional mode, the default behavior, to integration mode where the inputs and outputs of the component can be directly controlled for integration testing and topology solving.

Note: When a device has been in integration mode, it might not function with the original behavior. After performing integration or topology detection, you must reset the system to ensure correct behavior of CoreSight and other connected system components that are affected by the integration or topology detection.

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	INTEGRATIONMODE										Enables the component to switch from functional mode to integration mode and back. If no integration functionality is implemented, this register must read as zero.
			Disabled	0								Integration mode is disabled.
			Enabled	1								Integration mode is Enabled.

CLAIMSET

Address offset: 0xFA0

Software can use the claim tag to coordinate application and debugger access to trace unit functionality. The claim tags have no effect on the operation of the component. The CLAIMSET register sets bits in the claim tag, and determines the number of claim bits implemented.

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A-D	RW	BIT[i] (i=0..3)										Set claim bit i and check if bit is implemented or not.
			NotImplemented	0								Claim bit i is not implemented.
			Implemented	1								Claim bit i is implemented.
			Set	1								Set claim bit i.

CLAIMCLR

Address offset: 0xFA4

Software can use the claim tag to coordinate application and debugger access to trace unit functionality. The claim tags have no effect on the operation of the component. The CLAIMCLR register sets the bits in the claim tag to 0 and determines the current value of the claim tag.

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A-D	RW	BIT[i] (i=0..3)										Read or clear claim bit i.
			Cleared	0								Claim bit i is not set.
			Set	1								Claim bit i is set.
			Clear	1								Clear claim bit i.

LAR

Address offset: 0xFB0

This is used to enable write access to device registers.

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	ACCESS										A write of 0xC5ACCE55 enables further write access to this device. Any other write removes write access.
			UnLock	0xC5ACCE55								Unlock register interface.

LSR

Address offset: 0xFB4

This indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug. Accesses to the extended stimulus port registers are not affected by the lock mechanism. This register must always be present although there might not be any lock access control mechanism. The lock mechanism, where present and locked, must block write accesses to any control register, except the Lock Access Register. For most components this covers all registers except for the Lock Access Register.

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	PRESENT										Indicates that a lock control mechanism exists for this device.
			NotImplemented	0								No lock control mechanism exists, writes to the Lock Access Register are ignored.
			Implemented	1								Lock control mechanism is present.
B	RW	LOCKED										Returns the current status of the Lock.
			UnLocked	0								Write access is allowed to this device.
			Locked	1								Write access to the component is blocked. All writes to control registers are ignored. Reads are permitted.
C	RW	TYPE										Indicates if the Lock Access Register is implemented as 8-bit or 32-bit.
			Bits32	0								This component implements a 32-bit Lock Access Register.
			Bits8	1								This component implements an 8-bit Lock Access Register.

AUTHSTATUS

Address offset: 0xFB8

Indicates the current level of tracing permitted by the system

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																												D	D	C	C	B	B	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	NSID										Non-secure Invasive Debug
			NotImplemented	0								The feature is not implemented.
			Implemented	1								The feature is implemented.
B	RW	NSNID										Non-secure Non-Invasive Debug
			NotImplemented	0								The feature is not implemented.
			Implemented	1								The feature is implemented.
C	RW	SID										Secure Invasive Debug
			NotImplemented	0								The feature is not implemented.
			Implemented	1								The feature is implemented.
D	RW	SNID										Secure Non-Invasive Debug
			NotImplemented	0								The feature is not implemented.
			Implemented	1								The feature is implemented.

DEVID

Address offset: 0xFC8

Indicates the capabilities of the component.

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																								F	E	D	C	C	C	B	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	MUXNUM										Indicates the hidden level of input multiplexing. When non-zero, this value indicates the type of multiplexing on the input to the ATB. Currently only 0x00 is supported, that is, no multiplexing is present. This value helps detect the ATB structure.
B	R	CLKRELAT										Indicates the relationship between atclk and traceclkin.
			Synchronous	0								atclk and traceclkin are synchronous.
			ASynchronous	1								atclk and traceclkin are asynchronous.
C	R	FIFOSIZE										FIFO size in powers of 2.
			Entries4	2								FIFO size of 4 entries, that is, 16 bytes.
D	R	TCLKDATA										Indicates whether trace clock plus data is supported.
			Supported	0								Trace clock and data is supported.
			NotSupported	1								Trace clock and data is not supported.
E	R	SWOMAN										Indicates whether Serial Wire Output, Manchester encoded format, is supported.
			NotSupported	0								Serial Wire Output, Manchester encoded format, is not supported.
			Supported	1								Serial Wire Output, Manchester encoded format, is supported.
F	R	SWOUARTNRZ										Indicates whether Serial Wire Output, UART or NRZ, is supported.
			NotSupported	0								Serial Wire Output, UART or NRZ, is not supported.
			Supported	1								Serial Wire Output, UART or NRZ, is supported.

DEVTYPE

Address offset: 0xFCC

The DEVTYPE register provides a debugger with information about the component when the Part Number field is not recognized. The debugger can then report this information.

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																												B	B	B	B	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	MAJOR										The main type of the component
			TraceSource	1								Peripheral is a trace sink.
B	R	SUB										The sub-type of the component
			TracePort	1								Indicates that this component is a trace port component.