Clock management

The HFCLK clock controller provides several clocks in the system.

These are as follows:

• HCLK: 64 MHz CPU clock
• PCLK1M: 1 MHz peripheral clock
• PCLK16M: 16 MHz peripheral clock
• PCLK32M: 32 MHz peripheral clock

The HFCLK controller uses the following high frequency clock (HFCLK) sources:

• 64 MHz oscillator (HFINT)
• 64 MHz high accuracy oscillator (HFXO)

For illustration, see Clock and oscillator setup.

The HFCLK controller automatically provides the clock(s) requested by the system. If the system does not request any clocks from the HFCLK controller, the controller switches off all its clock sources and enters a power saving mode.

The HFINT source is used when HFCLK is requested and HFXO has not been started.

The HFXO is started by triggering the HFCLKSTART task and stopped using the HFCLKSTOP task. A HFCLKSTARTED event is generated when the HFXO has started and its frequency is stable.

The system supports several low frequency clock sources.

As illustrated in Clock and oscillator setup, the system supports the following low frequency clock sources:

• LFXO: 32.768 kHz high accuracy oscillator
• LFRC: 32.768 kHz RC oscillator

The LFCLK clock controller and all LFCLK clock sources are always switched off when in System OFF mode.

The LFCLK clock is started by first selecting the preferred clock source in the LFCLKSRC register and then triggering the LFCLKSTART task. LFXO is highly recommended as the LFCLK clock source, since the LFRC has a large frequency variation.

Switching between LFCLK clock sources can be done without stopping the LFCLK clock. A LFCLK clock source which is running prior to triggering the LFCLKSTART task continues to run until the selected clock source is available. After that the clock sources will be switched. Switching between clock sources will stretch a clock pulse by 0.5 to 1.0 clock cycle (i.e. will delay rising edge by 0.5 to 1.0 clock cycle).

A LFCLKSTARTED event will be generated when the selected LFCLK clock source has started.

A LFCLKSTOP task will prevent global requesting of the LFCLK clock, unless a system component such as WDT or modem requires the LFCLK, in which case the clock is not stopped. The LFCLKSTOP task should only be triggered after the STATE field in the LFCLKSTAT register indicates a LFCLK running state.