ETM — Embedded trace macrocell

The ARM embedded trace macorcell implements instruction, data and event tracing.

This document only provides a register-level description of this ARM component. See the Arm® Embedded Trace Macrocell Architecture Specification for more details

Registers

Instances

Instance Base address TrustZone Split access Description
Map Att DMA
ETM 0xE0041000 HF NS NA No

ETM

Register overview

Register Offset TZ Description
TRCPRGCTLR 0x004  

Enables the trace unit.

TRCPROCSELR 0x008  

Controls which PE to trace.

Might ignore writes when the trace unit is enabled or not idle.

Before writing to this register, ensure that TRCSTATR.IDLE == 1 so that the trace unit can synchronize with the chosen PE.

Implemented if TRCIDR3.NUMPROC is greater than zero.

TRCSTATR 0x00C  

Idle status bit

TRCCONFIGR 0x010  

Controls the tracing options

This register must always be programmed as part of trace unit initialization.

Might ignore writes when the trace unit is enabled or not idle.

TRCEVENTCTL0R 0x20  

Controls the tracing of arbitrary events.

If the selected event occurs a trace element is generated in the trace stream according to the settings in TRCEVENTCTL1R.DATAEN and TRCEVENTCTL1R.INSTEN.

TRCEVENTCTL1R 0x24  

Controls the behavior of the events that TRCEVENTCTL0R selects.

This register must always be programmed as part of trace unit initialization.

Might ignore writes when the trace unit is enabled or not idle.

TRCSTALLCTLR 0x2C  

Enables trace unit functionality that prevents trace unit buffer overflows.

Might ignore writes when the trace unit is enabled or not idle.

Must be programmed if TRCIDR3.STALLCTL == 1.

TRCTSCTLR 0x30  

Controls the insertion of global timestamps in the trace streams.

When the selected event is triggered, the trace unit inserts a global timestamp into the trace streams.

Might ignore writes when the trace unit is enabled or not idle.

Must be programmed if TRCCONFIGR.TS == 1.

TRCSYNCPR 0x34  

Controls how often trace synchronization requests occur.

Might ignore writes when the trace unit is enabled or not idle.

If writes are permitted then the register must be programmed.

TRCCCCTLR 0x38  

Sets the threshold value for cycle counting.

Might ignore writes when the trace unit is enabled or not idle.

Must be programmed if TRCCONFIGR.CCI==1.

TRCBBCTLR 0x3C  

Controls which regions in the memory map are enabled to use branch broadcasting.

Might ignore writes when the trace unit is enabled or not idle.

Must be programmed if TRCCONFIGR.BB == 1.

TRCTRACEIDR 0x40  

Sets the trace ID for instruction trace. If data trace is enabled then it also sets the trace ID for data trace, to (trace ID for instruction trace) + 1.

This register must always be programmed as part of trace unit initialization.

Might ignore writes when the trace unit is enabled or not idle.

TRCQCTLR 0x44  

Controls when Q elements are enabled.

Might ignore writes when the trace unit is enabled or not idle.

This register must be programmed if it is implemented and TRCCONFIGR.QE is set to any value other than 0b00.

TRCVICTLR 0x080  

Controls instruction trace filtering.

Might ignore writes when the trace unit is enabled or not idle.

Only returns stable data when TRCSTATR.PMSTABLE == 1.

Must be programmed, particularly to set the value of the SSSTATUS bit, which sets the state of the start/stop logic.

TRCVIIECTLR 0x084  

ViewInst exclude control.

Might ignore writes when the trace unit is enabled or not idle.

This register must be programmed when one or more address comparators are implemented.

TRCVISSCTLR 0x088  

Use this to set, or read, the single address comparators that control the ViewInst start/stop logic. The start/stop logic is active for an instruction which causes a start and remains active up to and including an instruction which causes a stop, and then the start/stop logic becomes inactive.

Might ignore writes when the trace unit is enabled or not idle.

If implemented then this register must be programmed.

TRCVIPCSSCTLR 0x08C  

Use this to set, or read, which PE comparator inputs can control the ViewInst start/stop logic.

Might ignore writes when the trace unit is enabled or not idle.

If implemented then this register must be programmed.

TRCVDCTLR 0x0A0  

Controls data trace filtering.

Might ignore writes when the trace unit is enabled or not idle.

This register must be programmed when data tracing is enabled, that is, when either TRCCONFIGR.DA == 1 or TRCCONFIGR.DV == 1.

TRCVDSACCTLR 0x0A4  

ViewData include / exclude control.

Might ignore writes when the trace unit is enabled or not idle.

This register must be programmed when one or more address comparators are implemented.

TRCVDARCCTLR 0x0A8  

ViewData include / exclude control.

Might ignore writes when the trace unit is enabled or not idle.

This register must be programmed when one or more address comparators are implemented.

TRCSEQEVR[n] 0x100  

Moves the sequencer state according to programmed events.

Might ignore writes when the trace unit is enabled or not idle.

When the sequencer is used, all sequencer state transitions must be programmed with a valid event.

TRCSEQRSTEVR 0x118  

Moves the sequencer to state 0 when a programmed event occurs.

Might ignore writes when the trace unit is enabled or not idle.

When the sequencer is used, all sequencer state transitions must be programmed with a valid event.

TRCSEQSTR 0x11C  

Use this to set, or read, the sequencer state.

Might ignore writes when the trace unit is enabled or not idle.

Only returns stable data when TRCSTATR.PMSTABLE == 1.

When the sequencer is used, all sequencer state transitions must be programmed with a valid event.

TRCEXTINSELR 0x120  

Use this to set, or read, which external inputs are resources to the trace unit.

Might ignore writes when the trace unit is enabled or not idle.

Only returns stable data when TRCSTATR.PMSTABLE == 1.

When the sequencer is used, all sequencer state transitions must be programmed with a valid event.

TRCCNTRLDVR[n] 0x140  

This sets or returns the reload count value for counter n.

Might ignore writes when the trace unit is enabled or not idle.

TRCCNTCTLR[n] 0x150  

Controls the operation of counter n.

Might ignore writes when the trace unit is enabled or not idle.

TRCCNTVR[n] 0x160  

This sets or returns the value of counter n.

The count value is only stable when TRCSTATR.PMSTABLE == 1.

If software uses counter n then it must write to this register to set the initial counter value.

Might ignore writes when the trace unit is enabled or not idle.

TRCRSCTLR[n] 0x200  

Controls the selection of the resources in the trace unit.

Might ignore writes when the trace unit is enabled or not idle.

If software selects a non-implemented resource then CONSTRAINED UNPREDICTABLE behavior of the resource selector occurs, so the resource selector might fire unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.

TRCSSCCR0 0x280  

Controls the single-shot comparator.

TRCSSCSR0 0x2A0  

Indicates the status of the single-shot comparators. TRCSSCSR0 is sensitive toinstruction addresses.

TRCSSPCICR0 0x2C0  

Selects the processor comparator inputs for Single-shot control.

TRCPDCR 0x310  

Controls the single-shot comparator.

TRCPDSR 0x314  

Indicates the power down status of the ETM.

TRCITATBIDR 0xEE4  

Sets the state of output pins.

TRCITIATBINR 0xEF4  

Reads the state of the input pins.

TRCITIATBOUTR 0xEFC  

Sets the state of the output pins.

TRCITCTRL 0xF00  

Enables topology detection or integration testing, by putting ETM-M33 into integration mode.

TRCCLAIMSET 0xFA0  

Sets bits in the claim tag and determines the number of claim tag bits implemented.

TRCCLAIMCLR 0xFA4  

Clears bits in the claim tag and determines the current value of the claim tag.

TRCAUTHSTATUS 0xFB8  

Indicates the current level of tracing permitted by the system

TRCDEVARCH 0xFBC  

The TRCDEVARCH identifies ETM-M33 as an ETMv4.2 component

TRCDEVTYPE 0xFCC  

Controls the single-shot comparator.

TRCPIDR[n] 0xFD0  

Coresight peripheral identification registers.

TRCCIDR[n] 0xFF0  

Coresight component identification registers.

TRCPRGCTLR

Address offset: 0x004

Enables the trace unit.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

EN

 

Trace unit enable bit

     

Disabled

0

The trace unit is disabled. All trace resources are inactive and no trace is generated.

     

Enabled

1

The trace unit is enabled.

TRCPROCSELR

Address offset: 0x008

Controls which PE to trace.

Might ignore writes when the trace unit is enabled or not idle.

Before writing to this register, ensure that TRCSTATR.IDLE == 1 so that the trace unit can synchronize with the chosen PE.

Implemented if TRCIDR3.NUMPROC is greater than zero.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                       A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

PROCSEL

 

PE select bits that select the PE to trace.

TRCSTATR

Address offset: 0x00C

Idle status bit

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                             B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

IDLE

 

Trace unit enable bit

     

NotIdle

0

The trace unit is not idle.

     

Idle

1

The trace unit is idle.

B

RW

PMSTABLE

 

Programmers' model stable bit

     

NotStable

0

The programmers' model is not stable.

     

Stable

1

The programmers' model is stable.

TRCCONFIGR

Address offset: 0x010

Controls the tracing options

This register must always be programmed as part of trace unit initialization.

Might ignore writes when the trace unit is enabled or not idle.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                             M L K J J I H G G G F E   D C B A  
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

LOADASP0INST

 

Instruction P0 load field. This field controls whether load instructions are traced as P0 instructions.

     

No

0

Do not trace load instructions as P0 instructions.

     

Yes

1

Trace load instructions as P0 instructions.

B

RW

STOREASP0INST

 

Instruction P0 field. This field controls whether store instructions are traced as P0 instructions.

     

No

0

Do not trace store instructions as P0 instructions.

     

Yes

1

Trace store instructions as P0 instructions.

C

RW

BB

 

Branch broadcast mode bit.

     

Disabled

0

Branch broadcast mode is disabled.

     

Enabled

1

Branch broadcast mode is enabled.

D

RW

CCI

 

Cycle counting instruction trace bit.

     

Disabled

0

Cycle counting in the instruction trace is disabled.

     

Enabled

1

Cycle counting in the instruction trace is enabled.

E

RW

CID

 

Context ID tracing bit.

     

Disabled

0

Context ID tracing is disabled.

     

Enabled

1

Context ID tracing is enabled.

F

RW

VMID

 

Virtual context identifier tracing bit.

     

Disabled

0

Virtual context identifier tracing is disabled.

     

Enabled

1

Virtual context identifier tracing is enabled.

G

RW

COND

 

Conditional instruction tracing bit.

     

Disabled

0

Conditional instruction tracing is disabled.

     

LoadOnly

1

Conditional load instructions are traced.

     

StoreOnly

2

Conditional store instructions are traced.

     

LoadAndStore

3

Conditional load and store instructions are traced.

     

All

7

All conditional instructions are traced.

H

RW

TS

 

Global timestamp tracing bit.

     

Disabled

0

Global timestamp tracing is disabled.

     

Enabled

1

Global timestamp tracing is enabled.

I

RW

RS

 

Return stack enable bit.

     

Disabled

0

Return stack is disabled.

     

Enabled

1

Return stack is enabled.

J

RW

QE

 

Q element enable field.

     

Disabled

0

Q elements are disabled.

     

OnlyWithoutInstCounts

1

Q elements with instruction counts are enabled. Q elements without instruction counts are disabled.

     

Enabled

3

Q elements with and without instruction counts are enabled.

K

RW

VMIDOPT

 

Control bit to select the Virtual context identifier value used by the trace unit, both for trace generation and in the Virtual context identifier comparators.

     

VTTBR_EL2

0

VTTBR_EL2.VMID is used. If the trace unit supports a Virtual context identifier larger than the VTTBR_EL2.VMID, the upper unused bits are always zero. If the trace unit supports a Virtual context identifier larger than 8 bits and if the VTCR_EL2.VS bit forces use of an 8-bit Virtual context identifier, bits [15:8] of the trace unit Virtual context identifier are always zero.

     

CONTEXTIDR_EL2

1

CONTEXTIDR_EL2 is used.

L

RW

DA

 

Data address tracing bit.

     

Disabled

0

Data address tracing is disabled.

     

Enabled

1

Data address tracing is enabled.

M

RW

DV

 

Data value tracing bit.

     

Disabled

0

Data value tracing is disabled.

     

Enabled

1

Data value tracing is enabled.

TRCEVENTCTL0R

Address offset: 0x20

Controls the tracing of arbitrary events.

If the selected event occurs a trace element is generated in the trace stream according to the settings in TRCEVENTCTL1R.DATAEN and TRCEVENTCTL1R.INSTEN.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                 A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

EVENT

[0:255]

Select which event should generate trace elements.

TRCEVENTCTL1R

Address offset: 0x24

Controls the behavior of the events that TRCEVENTCTL0R selects.

This register must always be programmed as part of trace unit initialization.

Might ignore writes when the trace unit is enabled or not idle.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                       G F             E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A-D

RW

INSTEN[i] (i=0..3)

 

Instruction event enable field.

     

Disabled

0

The trace unit does not generate an Event element.

     

Enabled

1

The trace unit generates an Event element for event i, in the instruction trace stream.

E

RW

DATAEN

 

Data event enable bit.

     

Disabled

0

The trace unit does not generate an Event element if event 0 occurs.

     

Enabled

1

The trace unit generates an Event element in the data trace stream if event 0 occurs.

F

RW

ATB

 

AMBA Trace Bus (ATB) trigger enable bit.

     

Disabled

0

ATB trigger is disabled.

     

Enabled

1

ATB trigger is enabled. If a CoreSight ATB interface is implemented then when event 0 occurs the trace unit generates an ATB event.

G

RW

LPOVERRIDE

 

Low-power state behavior override bit. Controls how a trace unit behaves in low-power state.

     

Disabled

0

Trace unit low-power state behavior is not affected. That is, the trace unit is enabled to enter low-power state.

     

Enabled

1

Trace unit low-power state behavior is overridden. That is, entry to a low-power state does not affect the trace unit resources or trace generation.

TRCSTALLCTLR

Address offset: 0x2C

Enables trace unit functionality that prevents trace unit buffer overflows.

Might ignore writes when the trace unit is enabled or not idle.

Must be programmed if TRCIDR3.STALLCTL == 1.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                     G F E D C B         A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

LEVEL

[15:0]

Threshold level field.

If LEVEL is nonzero then a trace unit might suppress the generation of:

Global timestamps in the instruction trace stream and the data trace stream.

Cycle counting in the instruction trace stream, although the cumulative cycle count remains correct.

     

Min

0

Zero invasion. This setting has a greater risk of a FIFO overflow

     

Max

15

Maximum invasion occurs but there is less risk of a FIFO overflow.

B

RW

ISTALL

 

Instruction stall bit. Controls if a trace unit can stall the PE when the instruction trace buffer space is less than LEVEL.

     

Disabled

0

The trace unit must not stall the PE.

     

Enabled

1

The trace unit can stall the PE.

C

RW

DSTALL

 

Data stall bit. Controls if a trace unit can stall the PE when the data trace buffer space is less than LEVEL.

     

Disabled

0

The trace unit must not stall the PE.

     

Enabled

1

The trace unit can stall the PE.

D

RW

INSTPRIORITY

 

Prioritize instruction trace bit. Controls if a trace unit can prioritize instruction trace when the instruction trace buffer space is less than LEVEL.

     

Disabled

0

The trace unit must not prioritize instruction trace.

     

Enabled

1

The trace unit can prioritize instruction trace. A trace unit might prioritize instruction trace by preventing output of data trace, or other means which ensure that the instruction trace has a higher priority than the data trace.

E

RW

DATADISCARDLOAD

 

Data discard field. Controls if a trace unit can discard data trace elements on a load when the data trace buffer space is less than LEVEL.

     

Disabled

0

The trace unit must not discard any data trace elements.

     

Enabled

1

The trace unit can discard P1 and P2 elements associated with data loads.

F

RW

DATADISCARDSTORE

 

Data discard field. Controls if a trace unit can discard data trace elements on a store when the data trace buffer space is less than LEVEL.

     

Disabled

0

The trace unit must not discard any data trace elements.

     

Enabled

1

The trace unit can discard P1 and P2 elements associated with data stores.

G

RW

NOOVERFLOW

 

Trace overflow prevention bit.

     

Disabled

0

Trace overflow prevention is disabled.

     

Enabled

1

Trace overflow prevention is enabled. This might cause a significant performance impact.

TRCTSCTLR

Address offset: 0x30

Controls the insertion of global timestamps in the trace streams.

When the selected event is triggered, the trace unit inserts a global timestamp into the trace streams.

Might ignore writes when the trace unit is enabled or not idle.

Must be programmed if TRCCONFIGR.TS == 1.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                 A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

EVENT

[0:255]

Select which event should generate time stamps.

TRCSYNCPR

Address offset: 0x34

Controls how often trace synchronization requests occur.

Might ignore writes when the trace unit is enabled or not idle.

If writes are permitted then the register must be programmed.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                       A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

PERIOD

[31:0]

Controls how many bytes of trace, the sum of instruction and data, that a trace unit can generate before a trace synchronization request occurs. The number of bytes is always a power of two, calculated by 2^PERIOD

     

Disabled

0

Trace synchronization requests are disabled. This setting does not disable other types of trace synchronization request.

TRCCCCTLR

Address offset: 0x38

Sets the threshold value for cycle counting.

Might ignore writes when the trace unit is enabled or not idle.

Must be programmed if TRCCONFIGR.CCI==1.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                         A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

THRESHOLD

[2047:0]

Sets the threshold value for instruction trace cycle counting.

TRCBBCTLR

Address offset: 0x3C

Controls which regions in the memory map are enabled to use branch broadcasting.

Might ignore writes when the trace unit is enabled or not idle.

Must be programmed if TRCCONFIGR.BB == 1.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                 H G F E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A-H

RW

RANGE[i] (i=0..7)

 

Address range field. Selects which address range comparator pairs are in use with branch broadcasting. Each field represents an address range comparator pair, so field[i] controls the selection of address range comparator pair i.

     

Disabled

0

The address range that address range comparator pair i defines, is not selected.

     

Enabled

1

The address range that address range comparator pair n defines, is selected.

TRCTRACEIDR

Address offset: 0x40

Sets the trace ID for instruction trace. If data trace is enabled then it also sets the trace ID for data trace, to (trace ID for instruction trace) + 1.

This register must always be programmed as part of trace unit initialization.

Might ignore writes when the trace unit is enabled or not idle.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                   A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

TRACEID

 

Trace ID field. Sets the trace ID value for instruction trace.

Bit[0] must be zero if data trace is enabled. If data trace is enabled then a trace unit sets the trace ID for data trace, to TRACEID+1.

TRCQCTLR

Address offset: 0x44

Controls when Q elements are enabled.

Might ignore writes when the trace unit is enabled or not idle.

This register must be programmed if it is implemented and TRCCONFIGR.QE is set to any value other than 0b00.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                               I H G F E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A-H

RW

RANGE[i] (i=0..7)

 

Specifies the address range comparators to be used for controlling Q elements.

     

Disabled

0

Address range comparator i is disabled.

     

Enabled

1

Address range comparator i is selected for use.

I

RW

MODE

 

Selects whether the address range comparators selected by the RANGE field indicate address ranges where the trace unit is permitted to generate Q elements or address ranges where the trace unit is not permitted to generate Q elements:

     

Exclude

0

Exclude mode. The address range comparators selected by the RANGE field indicate address ranges where the trace unit cannot generate Q elements. If no ranges are selected, Q elements are permitted across the entire memory map.

     

Include

1

Include mode. The address range comparators selected by the RANGE field indicate address ranges where the trace unit can generate Q elements. If all the implemented bits in RANGE are set to 0 then Q elements are disabled.

TRCVICTLR

Address offset: 0x080

Controls instruction trace filtering.

Might ignore writes when the trace unit is enabled or not idle.

Only returns stable data when TRCSTATR.PMSTABLE == 1.

Must be programmed, particularly to set the value of the SSSTATUS bit, which sets the state of the start/stop logic.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                 L K J I H G F E         D C B         A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

EVENT_SEL

 

Select which resource number should be filtered.

     

Disabled

0

This event is not filtered.

     

Enabled

1

This event is filtered.

B

RW

SSSTATUS

 

When TRCIDR4.NUMACPAIRS > 0 or TRCIDR4.NUMPC > 0, this bit returns the status of the start/stop logic.

     

Stopped

0

The start/stop logic is in the stopped state.

     

Started

1

The start/stop logic is in the started state.

C

RW

TRCRESET

 

Controls whether a trace unit must trace a Reset exception.

     

Disabled

0

The trace unit does not trace a Reset exception unless it traces the exception or instruction immediately prior to the Reset exception.

     

Enabled

1

The trace unit always traces a Reset exception.

D

RW

TRCERR

 

When TRCIDR3.TRCERR==1, this bit controls whether a trace unit must trace a System error exception.

     

Disabled

0

The trace unit does not trace a System error exception unless it traces the exception or instruction immediately prior to the System error exception.

     

Enabled

1

The trace unit always traces a System error exception, regardless of the value of ViewInst.

E-H

RW

EXLEVEL[i]_S (i=0..3)

 

In Secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level i.

     

Disabled

1

The trace unit does not generate instruction trace, in Secure state, for Exception level i.

     

Enabled

0

The trace unit generates instruction trace, in Secure state, for Exception level i.

I-L

RW

EXLEVEL[i]_NS (i=0..3)

 

In Non-secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level i.

     

Disabled

1

The trace unit does not generate instruction trace, in Non-secure state, for Exception level i.

     

Enabled

0

The trace unit generates instruction trace, in Non-secure state, for Exception level i.

TRCVIIECTLR

Address offset: 0x084

ViewInst exclude control.

Might ignore writes when the trace unit is enabled or not idle.

This register must be programmed when one or more address comparators are implemented.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                 P O N M L K J I                 H G F E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A-H

RW

INCLUDE[i] (i=0..7)

 

Include range field. Selects which address range comparator pairs are in use with ViewInst include control.

     

Disabled

0

The address range that address range comparator pair i defines, is not selected for ViewInst include control.

     

Enabled

1

The address range that address range comparator pair i defines, is selected for ViewInst include control.

I-P

RW

EXCLUDE[i] (i=0..7)

 

Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude control.

     

Disabled

0

The address range that address range comparator pair i defines, is not selected for ViewInst exclude control.

     

Enabled

1

The address range that address range comparator pair i defines, is selected for ViewInst exclude control.

TRCVISSCTLR

Address offset: 0x088

Use this to set, or read, the single address comparators that control the ViewInst start/stop logic. The start/stop logic is active for an instruction which causes a start and remains active up to and including an instruction which causes a stop, and then the start/stop logic becomes inactive.

Might ignore writes when the trace unit is enabled or not idle.

If implemented then this register must be programmed.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                 P O N M L K J I                 H G F E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A-H

RW

START[i] (i=0..7)

 

Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of starting trace.

     

Disabled

0

The single address comparator i, is not selected as a start resource.

     

Enabled

1

The single address comparator i, is selected as a start resource.

I-P

RW

STOP[i] (i=0..7)

 

Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of stopping trace

     

Disabled

0

The single address comparator i, is not selected as a stop resource.

     

Enabled

1

The single address comparator i, is selected as a stop resource.

TRCVIPCSSCTLR

Address offset: 0x08C

Use this to set, or read, which PE comparator inputs can control the ViewInst start/stop logic.

Might ignore writes when the trace unit is enabled or not idle.

If implemented then this register must be programmed.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                 P O N M L K J I                 H G F E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A-H

RW

START[i] (i=0..7)

 

Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting trace

     

Disabled

0

The single PE comparator input i, is not selected as a start resource.

     

Enabled

1

The single PE comparator input i, is selected as a start resource.

I-P

RW

STOP[i] (i=0..7)

 

Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping trace.

     

Disabled

0

The single PE comparator input i, is not selected as a stop resource.

     

Enabled

1

The single PE comparator input i, is selected as a stop resource.

TRCVDCTLR

Address offset: 0x0A0

Controls data trace filtering.

Might ignore writes when the trace unit is enabled or not idle.

This register must be programmed when data tracing is enabled, that is, when either TRCCONFIGR.DA == 1 or TRCCONFIGR.DV == 1.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                       L K J I I H G F E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A-H

RW

EVENT[i] (i=0..7)

 

Event unit enable bit.

     

Disabled

0

The trace event is not selected for trace filtering.

     

Enabled

1

The trace event is selected for trace filtering.

I

RW

SPREL

 

Controls whether a trace unit traces data for transfers that are relative to the Stack Pointer (SP).

     

Enabled

0

The trace unit does not affect the tracing of SP-relative transfers.

     

DataOnly

2

The trace unit does not trace the address portion of SP-relative transfers. If data value tracing is enabled then the trace unit generates a P1 data address element.

     

Disabled

3

The trace unit does not trace the address or value portions of SP-relative transfers.

J

RW

PCREL

 

Controls whether a trace unit traces data for transfers that are relative to the Program Counter (PC).

     

Enabled

0

The trace unit does not affect the tracing of PC-relative transfers.

     

Disabled

1

The trace unit does not trace the address or value portions of PC-relative transfers.

K

RW

TBI

 

Controls which information a trace unit populates in bits[63:56] of the data address.

     

SignExtend

0

The trace unit assigns bits[63:56] to have the same value as bit[55] of the data address, that is, it sign-extends the value.

     

Copy

1

The trace unit assigns bits[63:56] to have the same value as bits[63:56] of the data address.

L

RW

TRCEXDATA

 

Controls the tracing of data transfers for exceptions and exception returns on Armv6-M, Armv7-M, and Armv8-M PEs.

     

Disabled

0

Exception and exception return data transfers are not traced.

     

Enabled

1

Exception and exception return data transfers are traced if the other aspects of ViewData indicate that the data transfers must be traced.

TRCVDSACCTLR

Address offset: 0x0A4

ViewData include / exclude control.

Might ignore writes when the trace unit is enabled or not idle.

This register must be programmed when one or more address comparators are implemented.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                 P O N M L K J I                 H G F E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A-H

RW

INCLUDE[i] (i=0..7)

 

Selects which single address comparators are in use with ViewData include control.

     

Disabled

0

The single address comparator i, is not selected for ViewData include control.

     

Enabled

1

The single address comparator i, is selected for ViewData include control.

I-P

RW

EXCLUDE[i] (i=0..7)

 

Selects which single address comparators are in use with ViewData exclude control.

     

Disabled

0

The single address comparator i, is not selected for ViewData exclude control.

     

Enabled

1

The single address comparator i, s selected for ViewData exclude control.

TRCVDARCCTLR

Address offset: 0x0A8

ViewData include / exclude control.

Might ignore writes when the trace unit is enabled or not idle.

This register must be programmed when one or more address comparators are implemented.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                 P O N M L K J I                 H G F E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A-H

RW

INCLUDE[i] (i=0..7)

 

Include range field. Selects which address range comparator pairs are in use with ViewData include control.

     

Disabled

0

The address range that address range comparator i defines, is not selected for ViewData include control.

     

Enabled

1

The address range that address range comparator i defines, is selected for ViewData include control.

I-P

RW

EXCLUDE[i] (i=0..7)

 

Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude control.

     

Disabled

0

The address range that address range comparator i defines, is not selected for ViewData exclude control.

     

Enabled

1

The address range that address range comparator i defines, s selected for ViewData exclude control.

TRCSEQEVR[n] (n=0..2)

Address offset: 0x100 + (n × 0x4)

Moves the sequencer state according to programmed events.

Might ignore writes when the trace unit is enabled or not idle.

When the sequencer is used, all sequencer state transitions must be programmed with a valid event.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                 P O N M L K J I H G F E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A-H

RW

F[i] (i=0..7)

 

Forward field.

     

Disabled

0

The trace event does not affect the sequencer.

     

Enabled

1

When the event occurs then the sequencer state moves from state n to state n+1.

I-P

RW

B[i] (i=0..7)

 

Backward field.

     

Disabled

0

The trace event does not affect the sequencer.

     

Enabled

1

When the event occurs then the sequencer state moves from state n+1 to state n.

TRCSEQRSTEVR

Address offset: 0x118

Moves the sequencer to state 0 when a programmed event occurs.

Might ignore writes when the trace unit is enabled or not idle.

When the sequencer is used, all sequencer state transitions must be programmed with a valid event.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                 A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

EVENT

[0:255]

Select which event should reset the sequencer.

TRCSEQSTR

Address offset: 0x11C

Use this to set, or read, the sequencer state.

Might ignore writes when the trace unit is enabled or not idle.

Only returns stable data when TRCSTATR.PMSTABLE == 1.

When the sequencer is used, all sequencer state transitions must be programmed with a valid event.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                             A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

STATE

 

Sets or returns the state of the sequencer.

     

State0

0

The sequencer is in state 0.

     

State1

1

The sequencer is in state 1.

     

State2

2

The sequencer is in state 2.

     

State3

3

The sequencer is in state 3.

TRCEXTINSELR

Address offset: 0x120

Use this to set, or read, which external inputs are resources to the trace unit.

Might ignore writes when the trace unit is enabled or not idle.

Only returns stable data when TRCSTATR.PMSTABLE == 1.

When the sequencer is used, all sequencer state transitions must be programmed with a valid event.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A-D

RW

SEL[i] (i=0..3)

[0:255]

Each field in this collection selects an external input as a resource for the trace unit.

TRCCNTRLDVR[n] (n=0..3)

Address offset: 0x140 + (n × 0x4)

This sets or returns the reload count value for counter n.

Might ignore writes when the trace unit is enabled or not idle.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                 A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

VALUE

[0:65535]

Contains the reload value for counter n. When a reload event occurs for counter n then the trace unit copies the VALUEn field into counter n.

TRCCNTCTLR[n] (n=0..3)

Address offset: 0x150 + (n × 0x4)

Controls the operation of counter n.

Might ignore writes when the trace unit is enabled or not idle.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                             D C B B B B B B B B A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

CNTEVENT

[0:255]

Selects an event, that when it occurs causes counter n to decrement.

B

RW

RLDEVENT

[0:255]

Selects an event, that when it occurs causes a reload event for counter n.

C

RW

RLDSELF

 

Controls whether a reload event occurs for counter n, when counter n reaches zero.

     

Disabled

0

The counter is in Normal mode.

     

Enabled

1

The counter is in Self-reload mode.

D

RW

CNTCHAIN

 

For TRCCNTCTLR3 and TRCCNTCTLR1, this bit controls whether counter n decrements when a reload event occurs for counter n-1.

     

Disabled

0

Counter n does not decrement when a reload event for counter n-1 occurs.

     

Enabled

1

Counter n decrements when a reload event for counter n-1 occurs. This concatenates counter n and counter n-1, to provide a larger count value.

TRCCNTVR[n] (n=0..3)

Address offset: 0x160 + (n × 0x4)

This sets or returns the value of counter n.

The count value is only stable when TRCSTATR.PMSTABLE == 1.

If software uses counter n then it must write to this register to set the initial counter value.

Might ignore writes when the trace unit is enabled or not idle.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                 A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

VALUE

[0:65535]

Contains the count value of counter n.

TRCRSCTLR[n] (n=2..31)

Address offset: 0x200 + (n × 0x4)

Controls the selection of the resources in the trace unit.

Might ignore writes when the trace unit is enabled or not idle.

If software selects a non-implemented resource then CONSTRAINED UNPREDICTABLE behavior of the resource selector occurs, so the resource selector might fire unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

EN

 

Trace unit enable bit

     

Disabled

0

The trace unit is disabled. All trace resources are inactive and no trace is generated.

     

Enabled

1

The trace unit is enabled.

TRCSSCCR0

Address offset: 0x280

Controls the single-shot comparator.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID               A                                                
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

RST

 

Enables the single-shot comparator resource to be reset when it occurs, to enable another comparator match to be detected

     

Disabled

0

Multiple matches can not be detected.

     

Enabled

1

Multiple matches can occur.

TRCSSCSR0

Address offset: 0x2A0

Indicates the status of the single-shot comparators. TRCSSCSR0 is sensitive toinstruction addresses.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID E                                                       D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

INST

 

Instruction address comparator support

     

False

0

Single-shot instruction address comparisons not supported.

     

True

1

Single-shot instruction address comparisons supported.

B

RW

DA

 

Data address comparator support

     

False

0

Data address comparisons not supported.

     

True

1

Data address comparisons supported.

C

RW

DV

 

Data value comparator support

     

False

0

Data value comparisons not supported.

     

True

1

Data value comparisons supported.

D

RW

PC

 

Process counter value comparator support

     

False

0

Process counter value comparisons not supported.

     

True

1

Process counter value comparisons supported.

E

RW

STATUS

 

Single-shot status. This indicates whether any of the selected comparators have matched.

     

NoMatch

0

Match has not occurred.

     

Match

1

Match has occurred at least once.

TRCSSPCICR0

Address offset: 0x2C0

Selects the processor comparator inputs for Single-shot control.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                         D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A-D

RW

PC[i] (i=0..3)

 

Selects processor comparator i inputs for Single-shot control

     

Disabled

0

Processor comparator i is not selected for Single-shot control.

     

Enabled

1

Processor comparator i is selected for Single-shot control.

TRCPDCR

Address offset: 0x310

Controls the single-shot comparator.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID               A                                                
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

PU

 

Power up request, to request that power to ETM and access to the trace registers is maintained.

     

Disabled

0

Power not requested.

     

Enabled

1

Power requested.

TRCPDSR

Address offset: 0x314

Indicates the power down status of the ETM.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                             B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

POWER

 

Indicates ETM is powered up

     

NotPoweredUp

0

ETM is not powered up. All registers are not accessible.

     

PoweredUp

1

ETM is powered up. All registers are accessible.

B

RW

STICKYPD

 

Sticky power down state.

This bit is set to 1 when power to the ETM registers is removed, to indicate that programming state has been lost. It is cleared after a read of the TRCPDSR

     

NotPoweredDown

0

Trace register power has not been removed since the TRCPDSR was last read.

     

PoweredDown

1

Trace register power has been removed since the TRCPDSR was last read.

TRCITATBIDR

Address offset: 0xEE4

Sets the state of output pins.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                   G F E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A-G

RW

ID[i] (i=0..