ETB — Embedded trace buffer

Address offset: 0x4

ETB RAM Depth Register

Defines the depth, in words, of the trace RAM. This value is configurable in the RTL, but fixed at synthesis. Supported depth in powers of 2 only.

Address offset: 0xC

ETB Status Register

This register indicates the status of the ETB.

Address offset: 0x10

ETB RAM Read Data Register

When trace capture is disabled, the contents of the ETB Trace RAM at the location addressed by the RAM Read Pointer Registers are placed in this register. Reading this register increments the RAM Read Pointer Register and triggers a RAM access cycle. If trace capture is enabled (FtStopped=0, TraceCaptEn=1), and ETB RAM reading is attempted, a read from this register outputs 0xFFFFFFFF and the RAM Read Pointer Register does not auto-increment. A constant stream of 1s being output corresponds to a synchronization output in the formatter protocol, which is not applicable to the ETB, and so can be used to signify a read error, when formatting is enabled.

Address offset: 0x14

ETB RAM Read Pointer Register

The RAM Read Pointer Register sets the read pointer used to read entries from the Trace RAM over the APB interface. When this register is written to, a RAM access is initiated. The RAM Read Data Register is then updated. The register can also be read to determine the current memory location being referenced. This register must not be written to when trace capture is enabled (FtStopped=0, TraceCaptEn=1). If access is attempted, the register is not updated.

Address offset: 0x18

ETB RAM Write Pointer Register

The RAM Write Pointer Register sets the write pointer used to write entries from the CoreSight bus into Trace RAM. During trace capture the pointer increments when the DataValid flag is asserted by the Formatter. When this register increments from its maximum value back to zero, the Full flag is set. This register can also be written to over APB to set the pointer for write accesses carried out through the APB interface. This register must not be written to when trace capture is enabled (FtStopped=0, TraceCaptEn=1). If access is attempted, the register is not updated. The register can also be read to determine the current memory location being referenced. It is recommended that addresses are 128-bit aligned when the formatter is used in normal or continuous modes.

Address offset: 0x1C

ETB Trigger Counter Register

The Trigger Counter Register disables write access to the Trace RAM by stopping the Formatter after a defined number of words have been stored following the trigger event. The number of 32-bit words written into the Trace RAM following the trigger event is equal to the value stored in this register+1.

Address offset: 0x20

ETB Control Register

This register controls trace capture by the ETB.

Address offset: 0x24

ETB RAM Write Data Register

Data written to the ETB Trace RAM.

Address offset: 0x300

ETB Formatter and Flush Status Register

This register indicates the implemented Trigger Counter multipliers and other supported features of the trigger system.

Address offset: 0x304

ETB Formatter and Flush Control Register

This register controls the generation of stop, trigger, and flush events. To disable formatting and put the formatter into bypass mode, bits 1 and 0 must be clear. If both bits are set, then the formatter inserts triggers into the formatted stream. All three flush generating conditions can be enabled together. However, if a second or third flush event is generated then the current flush completes before the next flush is serviced. Flush from flushin takes priority over flush from Trigger, which in turn completes before a manually activated flush. All Trigger indication conditions can be enabled simultaneously although this can cause the appearance of multiple triggers if flush using trigger is also enabled. Both 'Stop On' settings can be enabled, although if flush on trigger, FOnTrig, is set up then none of the flushed data is stored. When the system stops, it returns ATREADY and does not store the accepted data packets. This is to avoid stalling of any other connected devices using a Trace Replicator. If an event in the Formatter and Flush Control Register is required, it must be enabled before the originating event starts. Because requests from flushes and triggers can originate in an asynchronous clock domain, the exact time the component acts on the request cannot be determined with respect to configuring the control. Note - To perform a stop on flush completion through a manually-generated flush request, two write operations to the register are required: one to enable the stop event, if it is not already enabled; one to generate the manual flush.

Address offset: 0xEE0

Integration Test Miscellaneous Output Register 0

The Integration Test Miscellaneous Output Register 0 controls the values of some outputs from the ETB.

Address offset: 0xEE4

Integration Test Trigger In and Flush In Acknowledge Register

The Integration Test Trigger In and Flush In Acknowledge Register enables control of the triginack and flushinack outputs from the ETB.

Address offset: 0xEE8

Integration Test Trigger In and Flush In Register

The Integration Test Trigger In and Flush In Register contains the values of the flushin and trigin inputs to the ETB.

Address offset: 0xEEC

Integration Test ATB Data Register 0

The Integration Test ATB Data Register 0 contains the value of the atdatas inputs to the ETB. The values are only valid when atvalids is HIGH.

Address offset: 0xEF0

Integration Test ATB Control Register 2

The Integration Test ATB Control Register 2 enables control of the atreadys and afvalids outputs of the ETB.

Address offset: 0xEF4

Integration Test ATB Control Register 1

The Integration Test ATB Control Register 1 contains the value of the atids input to the ETB. This is only valid when atvalids is HIGH.

Address offset: 0xEF8

Integration Test ATB Control Register 0

The Integration Test ATB Control Register 0 captures the values of the atvalids, afreadys, and atbytess inputs to the ETB. To ensure the integration registers work correctly in a system, the value of atbytess is only valid when atvalids, bit [0], is HIGH.

Address offset: 0xF00

Integration Mode Control Register

This register is used to enable topology detection. For more information see the CoreSight Architecture Specification. This register enables the component to switch from a functional mode, the default behavior, to integration mode where the inputs and outputs of the component can be directly controlled for the purpose of integration testing and topology solving. Note: When a device has been in integration mode, it might not function with the original behavior. After performing integration or topology detection, you must reset the system to ensure correct behavior of CoreSight and other connected system components that are affected by the integration or topology detection.

Address offset: 0xFA0

Claim Tag Set Register

This is used in conjunction with Claim Tag Clear Register, CLAIMCLR. This register forms one half of the Claim Tag value. This location allows individual bits to be set, write, and returns the number of bits that can be set, read.

Address offset: 0xFA4

Claim Tag Clear Register

This register is used in conjunction with Claim Tag Set Register, CLAIMSET. This register forms one half of the Claim Tag value. This location enables individual bits to be cleared, write, and returns the current Claim Tag value, read.

Address offset: 0xFB0

Lock Access Register

This is used to enable write access to device registers. External accesses from a debugger (paddrdbg31 = 1) are not subject to the Lock Registers. A debugger does not have to unlock the component in order to write and modify the registers in the component.

Address offset: 0xFB4

Lock Status Register

This indicates the status of the Lock control mechanism. This lock prevents accidental writes by code under debug. When locked, write access is blocked to all registers, except the Lock Access Register. External accesses from a debugger (paddrdbg31 = 1) are not subject to the Lock Registers. This register reads as 0 when read from an external debugger (paddrdbg31 = 1).

Address offset: 0xFB8

Authentication Status Register

Reports what functionality is currently permitted by the authentication interface.

Address offset: 0xFC8

Device Configuration Register

This register indicates the capabilities of the ETB.

Address offset: 0xFCC

Device Type Identifier Register

It provides a debugger with information about the component when the Part Number field is not recognized. The debugger can then report this information.

Address offset: 0xFD0

Peripheral ID4 Register

Part of the set of Peripheral Identification registers. Contains part of the designer identity and the memory footprint indicator.

Address offset: 0xFE0

Peripheral ID0 Register

Part of the set of Peripheral Identification registers. Contains part of the designer specific part number.

Address offset: 0xFE4

Peripheral ID1 Register

Part of the set of Peripheral Identification registers. Contains part of the designer specific part number and part of the designer identity.

Address offset: 0xFE8

Peripheral ID2 Register

Part of the set of Peripheral Identification registers. Contains part of the designer identity and the product revision.

Address offset: 0xFEC

Peripheral ID3 Register

Part of the set of Peripheral Identification registers. Contains the RevAnd and Customer Modified fields.

Address offset: 0xFF0

Component ID0 Register

A component identification register, that indicates that the identification registers are present.

Address offset: 0xFF4

Component ID1 Register

A component identification register, that indicates that the identification registers are present. This register also indicates the component class.

Address offset: 0xFF8

Component ID2 Register

A component identification register, that indicates that the identification registers are present.

Address offset: 0xFFC

Component ID3 Register

A component identification register, that indicates that the identification registers are present.