ATB Replicator

The ARM® ATB Replicator replicates incoming trace bus mesages across its outputs.

This document only provides a register-level description of this ARM component. See the ARM® CoreSight™ SoC-400 Technical Reference Manual for more details

Registers

Instances

Instance Base address TrustZone Split access Description
Map Att DMA
ATBREPLICATOR 0xE0058000 HF NS NA No

ATBREPLICATOR

Register overview

Register Offset TZ Description
IDFILTER0 0x000  

The IDFILTER0 register enables the programming of ID filtering for master port 0.

IDFILTER1 0x004  

The IDFILTER1 register enables the programming of ID filtering for master port 1.

ITATBCTR1 0xEF8  

The ITATBCTR1 register returns the value of the atreadym0, atreadym1, and atvalids inputs in integration mode.

ITATBCTR0 0xEFC  

The ITATBCTR0 register controls the value of the atvalidm0, atvalidm1, and atreadys outputs in integration mode.

ITCTRL 0xF00  

The ITCTRL register enables the component to switch from a functional mode, which is the default behavior, to integration mode where the inputs and outputs of the component can be directly controlled for the purposes of integration testing and topology detection.

CLAIMSET 0xFA0  

Software can use the claim tag to coordinate application and debugger access to trace unit functionality. The claim tags have no effect on the operation of the component. The CLAIMSET register sets bits in the claim tag, and determines the number of claim bits implemented.

CLAIMCLR 0xFA4  

Software can use the claim tag to coordinate application and debugger access to trace unit functionality. The claim tags have no effect on the operation of the component. The CLAIMCLR register sets the bits in the claim tag to 0 and determines the current value of the claim tag.

LAR 0xFB0  

This is used to enable write access to device registers.

LSR 0xFB4  

This indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug. Accesses to the extended stimulus port registers are not affected by the lock mechanism. This register must always be present although there might not be any lock access control mechanism. The lock mechanism, where present and locked, must block write accesses to any control register, except the Lock Access Register. For most components this covers all registers except for the Lock Access Register.

AUTHSTATUS 0xFB8  

Indicates the current level of tracing permitted by the system

DEVID 0xFC8  

Indicates the capabilities of the component.

DEVTYPE 0xFCC  

The DEVTYPE register provides a debugger with information about the component when the Part Number field is not recognized. The debugger can then report this information.

PIDR4 0xFD0  

Coresight peripheral identification registers.

PIDR[0] 0xFE0  

Coresight peripheral identification registers.

PIDR[1] 0xFE4  

Coresight peripheral identification registers.

PIDR[2] 0xFE8  

Coresight peripheral identification registers.

PIDR[3] 0xFEC  

Coresight peripheral identification registers.

CIDR[0] 0xFF0  

Coresight component identification registers.

CIDR[1] 0xFF4  

Coresight component identification registers.

CIDR[2] 0xFF8  

Coresight component identification registers.

CIDR[3] 0xFFC  

Coresight component identification registers.

IDFILTER0

Address offset: 0x000

The IDFILTER0 register enables the programming of ID filtering for master port 0.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                 H G F E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A-H

RW

ID0_[i]0_[i]F (i=0..7)

 

Enable or disable ID filtering for IDs 0xi0_0xiF.

     

NotFiltered

0

Transactions with these IDs are passed on to ATB master port 0.

     

Selected

1

Transactions with these IDs are discarded by the replicator.

IDFILTER1

Address offset: 0x004

The IDFILTER1 register enables the programming of ID filtering for master port 1.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                 H G F E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A-H

RW

ID1_[i]0_[i]F (i=0..7)

 

Enable or disable ID filtering for IDs 0xi0_0xiF.

     

NotFiltered

0

Transactions with these IDs are passed on to ATB master port 1.

     

Selected

1

Transactions with these IDs are discarded by the replicator.

ITATBCTR1

Address offset: 0xEF8

The ITATBCTR1 register returns the value of the atreadym0, atreadym1, and atvalids inputs in integration mode.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                         C   B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

ATREADYM0

 

Reads the value of the atreadym0 input.

     

Low

0

Pin is logic 0.

     

High

1

Pin is logic 1.

B

RW

ATREADYM1

 

Reads the value of the atreadym1 input.

     

Low

0

Pin is logic 0.

     

High

1

Pin is logic 1.

C

RW

ATVALIDS

 

Reads the value of the atvalids input.

     

Low

0

Pin is logic 0.

     

High

1

Pin is logic 1.

ITATBCTR0

Address offset: 0xEFC

The ITATBCTR0 register controls the value of the atvalidm0, atvalidm1, and atreadys outputs in integration mode.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                         C B   A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

ATVALIDM0

 

Sets the value of the atvalidm0 output.

     

Low

0

Pin is logic 0.

     

High

1

Pin is logic 1.

B

RW

ATVALIDM1

 

Sets the value of the atvalidm1 output.

     

Low

0

Pin is logic 0.

     

High

1

Pin is logic 1.

C

RW

ATREADYS

 

Sets the value of the atreadys output.

     

Low

0

Pin is logic 0.

     

High

1

Pin is logic 1.

ITCTRL

Address offset: 0xF00

The ITCTRL register enables the component to switch from a functional mode, which is the default behavior, to integration mode where the inputs and outputs of the component can be directly controlled for the purposes of integration testing and topology detection.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

IME

 

Integration Mode Enable.

     

Disabled

0

Integration mode disabled.

     

Enabled

1

Integration mode enabled.

CLAIMSET

Address offset: 0xFA0

Software can use the claim tag to coordinate application and debugger access to trace unit functionality. The claim tags have no effect on the operation of the component. The CLAIMSET register sets bits in the claim tag, and determines the number of claim bits implemented.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                         D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A-D

RW

BIT[i] (i=0..3)

 

Set claim bit i and check if bit is implemented or not.

     

NotImplemented

0

Claim bit i is not implemented.

     

Implemented

1

Claim bit i is implemented.

     

Set

1

Set claim bit i.

CLAIMCLR

Address offset: 0xFA4

Software can use the claim tag to coordinate application and debugger access to trace unit functionality. The claim tags have no effect on the operation of the component. The CLAIMCLR register sets the bits in the claim tag to 0 and determines the current value of the claim tag.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                         D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A-D

RW

BIT[i] (i=0..3)

 

Read or clear claim bit i.

     

Cleared

0

Claim bit i is not set.

     

Set

1

Claim bit i is set.

     

Clear

1

Clear claim bit i.

LAR

Address offset: 0xFB0

This is used to enable write access to device registers.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

ACCESS

 

A write of 0xC5ACCE55 enables further write access to this device. Any other write removes write access.

     

UnLock

0xC5ACCE55

Unlock register interface.

LSR

Address offset: 0xFB4

This indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug. Accesses to the extended stimulus port registers are not affected by the lock mechanism. This register must always be present although there might not be any lock access control mechanism. The lock mechanism, where present and locked, must block write accesses to any control register, except the Lock Access Register. For most components this covers all registers except for the Lock Access Register.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                           C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

PRESENT

 

Indicates that a lock control mechanism exists for this device.

     

NotImplemented

0

No lock control mechanism exists, writes to the Lock Access Register are ignored.

     

Implemented

1

Lock control mechanism is present.

B

RW

LOCKED

 

Returns the current status of the Lock.

     

UnLocked

0

Write access is allowed to this device.

     

Locked

1

Write access to the component is blocked. All writes to control registers are ignored. Reads are permitted.

C

RW

TYPE

 

Indicates if the Lock Access Register is implemented as 8-bit or 32-bit.

     

Bits32

0

This component implements a 32-bit Lock Access Register.

     

Bits8

1

This component implements an 8-bit Lock Access Register.

AUTHSTATUS

Address offset: 0xFB8

Indicates the current level of tracing permitted by the system

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                 D D C C B B A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

RW

NSID

 

Non-secure Invasive Debug

     

NotImplemented

0

The feature is not implemented.

     

Implemented

1

The feature is implemented.

B

RW

NSNID

 

Non-secure Non-Invasive Debug

     

NotImplemented

0

The feature is not implemented.

     

Implemented

1

The feature is implemented.

C

RW

SID

 

Secure Invasive Debug

     

NotImplemented

0

The feature is not implemented.

     

Implemented

1

The feature is implemented.

D

RW

SNID

 

Secure Non-Invasive Debug

     

NotImplemented

0

The feature is not implemented.

     

Implemented

1

The feature is implemented.

DEVID

Address offset: 0xFC8

Indicates the capabilities of the component.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                         A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

R

PORTNUM

[0:15]

Indicates the number of master ports implemented.

DEVTYPE

Address offset: 0xFCC

The DEVTYPE register provides a debugger with information about the component when the Part Number field is not recognized. The debugger can then report this information.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                 B B B B A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
A

R

MAJOR

 

The main type of the component

     

InputOutputDevice

2

Indicates that this component has ATB inputs and outputs.

B

R

SUB

 

The sub-type of the component

     

Replicator

2

Indicates that this component replicates trace from a single source to multiple targets.

PIDR4

Address offset: 0xFD0

Coresight peripheral identification registers.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                                
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
 

PIDR[0]

Address offset: 0xFE0

Coresight peripheral identification registers.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                                
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
 

PIDR[1]

Address offset: 0xFE4

Coresight peripheral identification registers.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                                
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
 

PIDR[2]

Address offset: 0xFE8

Coresight peripheral identification registers.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                                
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
 

PIDR[3]

Address offset: 0xFEC

Coresight peripheral identification registers.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                                
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
 

CIDR[0]

Address offset: 0xFF0

Coresight component identification registers.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                                
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
 

CIDR[1]

Address offset: 0xFF4

Coresight component identification registers.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                                
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
 

CIDR[2]

Address offset: 0xFF8

Coresight component identification registers.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                                
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description
 

CIDR[3]

Address offset: 0xFFC

Coresight component identification registers.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                                
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID R/W Field Value ID Value Description