This section describes the pin assignment and the pin functions.
This device provides flexibility when it comes to routing and configuration of the GPIO pins. However, some pins have recommendations for how the pin should be configured or what it should be used for. See LGA pin assignments for more information about this.
The pin assignment table and figure describe the assignments.
Pin no | Pin name | Function | Description |
---|---|---|---|
1 | GND_Shield | Power | Ground |
2 | P0.05 | Digital I/O (SoC) | General purpose I/O |
3 | P0.06 | Digital I/O (SoC) | General purpose I/O |
4 | P0.07 | Digital I/O (SoC) | General purpose I/O |
5 | GND_Shield | Power | Ground |
6 | GND_Shield | Power | Ground |
7 | GND_Shield | Power | Ground |
8 | GND_Shield | Power | Ground |
9 | GND_Shield | Power | Ground |
10 | Reserved | Do not connect/reserved for future use | |
11 | GND_Shield | Power | Ground |
12 | VDD_GPIO | Power | GPIO power supply input and logic level |
13 | DEC0 | Power | Power supply decoupling. Reserved for Nordic use. |
14 | GND_Shield | Power | Ground |
15 | P0.08 | Digital I/O (SoC) | General purpose I/O |
16 | P0.09 | Digital I/O (SoC) | General purpose I/O |
17 | GND_Shield | Power | Ground |
18 | P0.10 | Digital I/O (SoC) | General purpose I/O |
19 | P0.11 | Digital I/O (SoC) | General purpose I/O |
20 | P0.12 | Digital I/O (SoC) | General purpose I/O |
21 | GND_Shield | Power | Ground |
22 | VDD2 | Power | Supply voltage input |
23 |
P0.13 AIN0 |
Digital I/O (SoC) Analog input |
General purpose I/O. Analog input. |
24 |
P0.14 AIN1 |
Digital I/O (SoC) Analog input |
General purpose I/O. Analog input. |
25 |
P0.15 AIN2 |
Digital I/O (SoC) Analog input |
General purpose I/O. Analog input. |
26 |
P0.16 AIN3 |
Digital I/O (SoC) Analog input |
General purpose I/O. Analog input. |
27 | GND_Shield | Power | Ground |
28 |
P0.17 AIN4 |
Digital I/O (SoC) Analog input |
General purpose I/O. Analog input. |
29 |
P0.18 AIN5 |
Digital I/O (SoC) Analog input |
General purpose I/O. Analog input. |
30 |
P0.19 AIN6 |
Digital I/O (SoC) Analog input |
General purpose I/O. Analog input. |
31 | GND_Shield | Power | Ground |
32 | nRESET | Digital I/O (SoC) |
SoC system reset Note: External pull-up not allowed.
|
33 | SWDCLK | Digital input | Serial wire debug clock input for debug and programming |
34 | SWDIO | Digital I/O | Serial wire debug I/O for debug and programming |
35 |
P0.20 AIN7 |
Digital I/O (SoC) Analog input |
General purpose I/O. Analog input. |
36 | GND_Shield | Power | Ground |
37 |
P0.21 TRACECLK |
Digital I/O (SoC) Trace clock |
General purpose I/O. Trace buffer clock (optional). |
38 |
P0.22 TRACEDATA0 |
Digital I/O (SoC) Trace data |
General purpose I/O. Trace buffer TRACEDATA[0] (optional). |
39 |
P0.23 TRACEDATA1 |
Digital I/O (SoC) Trace data |
General purpose I/O. Trace buffer TRACEDATA[1] (optional). |
40 |
P0.24 TRACEDATA2 |
Digital I/O (SoC) Trace data |
General purpose I/O. Trace buffer TRACEDATA[2] (optional). |
41 | GND_Shield | Power | Ground |
42 |
P0.25 TRACEDATA3 |
Digital I/O (SoC) Trace data |
General purpose I/O. Trace buffer TRACEDATA[3] (optional). |
43 | SIM_RST | Digital I/O (SoC) | SIM reset |
44 | GND_Shield | Power | Ground |
45 | SIM_DET | Digital I/O (SoC) | SIM detect Not used. Needs to be left floating. |
46 | SIM_CLK | Digital I/O (SoC) | SIM clock |
47 | GND_Shield | Power | Ground |
48 | SIM_IO | Digital I/O (SoC) | SIM data |
49 | SIM_1V8 | Power | SIM 1.8 V power supply output |
50 | GND_Shield | Power | Ground |
51 | Reserved | Do not connect/reserved for future use | |
52 | GND_Shield | Power | Ground |
53 | MAGPIO2 | Digital I/O (SoC) | 1.8 V general purpose I/O |
54 | MAGPIO1 | Digital I/O (SoC) | 1.8 V general purpose I/O |
55 | MAGPIO0 | Digital I/O (SoC) | 1.8 V general purpose I/O |
56 | GND_Shield | Power | Ground |
57 | VIO | Power | MIPI RFFE control interface |
58 | SCLK | Digital I/O (SoC) | MIPI RFFE control interface |
59 | SDATA | Digital I/O (SoC) | MIPI RFFE control interface |
60 | GND_Shield | Power | Ground |
61 | ANT | RF | Single-ended 50 Ω LTE antenna pin |
62 | GND_Shield | Power | Ground |
63 | GND_Shield | Power | Ground |
64 | AUX | RF | Single-ended 50 Ω ANT loop-back pin |
65 | GND_Shield | Power | Ground |
66 | GND_Shield | Power | Ground |
67 | GPS | RF | Single-ended 50 Ω GPS input pin |
68 | GND_Shield | Power | Ground |
69 | GND_Shield | Power | Ground |
70 | Reserved | Do not connect/reserved for future use | |
71 | Reserved | Do not connect/reserved for future use | |
72 | GND_Shield | Power | Ground |
73 | Reserved | Do not connect/reserved for future use | |
74 | GND_Shield | Power | Ground |
75 | GND_Shield | Power | Ground |
76 | GND_Shield | Power | Ground |
77 | GND_Shield | Power | Ground |
78 | GND_Shield | Power | Ground |
79 | GND_Shield | Power | Ground |
80 | GND_Shield | Power | Ground |
81 | GND_Shield | Power | Ground |
82 | GND_Shield | Power | Ground |
83 | P0.26 | Digital I/O (SoC) | General purpose I/O |
84 | P0.27 | Digital I/O (SoC) | General purpose I/O |
85 | GND_Shield | Power | Ground |
86 | P0.28 | Digital I/O (SoC) | General purpose I/O |
87 | P0.29 | Digital I/O (SoC) | General purpose I/O |
88 | P0.30 | Digital I/O (SoC) | General purpose I/O |
89 | P0.31 | Digital I/O (SoC) | General purpose I/O |
90 | GND_Shield | Power | Ground |
91 | COEX2 | Digital I/O (SoC) | Coexistence interface |
92 | COEX1 | Digital I/O (SoC) | Coexistence interface |
93 | COEX0 | Digital I/O (SoC) | Coexistence interface |
94 | GND_Shield | Power | Ground |
95 | P0.00 | Digital I/O (SoC) | General purpose I/O |
96 | P0.01 | Digital I/O (SoC) | General purpose I/O |
97 | P0.02 | Digital I/O (SoC) | General purpose I/O |
98 | GND_Shield | Power | Ground |
99 | P0.03 | Digital I/O (SoC) | General purpose I/O |
100 | P0.04 | Digital I/O (SoC) | General purpose I/O |
101 | ENABLE |
Enable for the SiP internal regulator for the nRF91 SoC. Note: The nRF91 will not start until this pin is enabled.
|
|
102 | VDD1 | Power | Supply voltage |
103 | VSS | Power | Ground |
104-127 | Reserved | Do not connect/reserved for future use |