TAD - Trace and debug control

Configuration interface for trace and debug

Registers

Table 1. Instances
Base address Peripheral Instance Secure mapping DMA security Description Configuration
0xE0080000 TAD TAD S NA

Trace and debug control

   
Table 2. Register overview
Register Offset Security Description
ENABLE 0x500  

Enable debug domain and aquire selected GPIOs

 
PSEL.TRACECLK 0x504  

Pin number configuration for TRACECLK

 
PSEL.TRACEDATA0 0x508  

Pin number configuration for TRACEDATA[0]

 
PSEL.TRACEDATA1 0x50C  

Pin number configuration for TRACEDATA[1]

 
PSEL.TRACEDATA2 0x510  

Pin number configuration for TRACEDATA[2]

 
PSEL.TRACEDATA3 0x514  

Pin number configuration for TRACEDATA[3]

 
TRACEPORTSPEED 0x518  

Clocking options for the Trace Port debug interface

 

ENABLE

Address offset: 0x500

Enable debug domain and aquire selected GPIOs

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

ENABLE

     

     

DISABLED

0

Disable debug domain and release selected GPIOs

     

ENABLED

1

Enable debug domain and aquire selected GPIOs

PSEL.TRACECLK

Address offset: 0x504

Pin number configuration for TRACECLK

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                     A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID Access Field Value ID Value Description
A RW

PIN

 

[0..31]

Pin number

B RW

CONNECT

   

Connection

     

Disconnected

1

Disconnect

     

Connected

0

Connect

PSEL.TRACEDATA0

Address offset: 0x508

Pin number configuration for TRACEDATA[0]

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                     A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID Access Field Value ID Value Description
A RW

PIN

 

[0..31]

Pin number

B RW

CONNECT

   

Connection

     

Disconnected

1

Disconnect

     

Connected

0

Connect

PSEL.TRACEDATA1

Address offset: 0x50C

Pin number configuration for TRACEDATA[1]

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                     A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID Access Field Value ID Value Description
A RW

PIN

 

[0..31]

Pin number

B RW

CONNECT

   

Connection

     

Disconnected

1

Disconnect

     

Connected

0

Connect

PSEL.TRACEDATA2

Address offset: 0x510

Pin number configuration for TRACEDATA[2]

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                     A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID Access Field Value ID Value Description
A RW

PIN

 

[0..31]

Pin number

B RW

CONNECT

   

Connection

     

Disconnected

1

Disconnect

     

Connected

0

Connect

PSEL.TRACEDATA3

Address offset: 0x514

Pin number configuration for TRACEDATA[3]

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID B                                                     A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID Access Field Value ID Value Description
A RW

PIN

 

[0..31]

Pin number

B RW

CONNECT

   

Connection

     

Disconnected

1

Disconnect

     

Connected

0

Connect

TRACEPORTSPEED

Address offset: 0x518

Clocking options for the Trace Port debug interface

This register is a retained register. Reset behavior is the same as debug components.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                             A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

TRACEPORTSPEED

   

Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two.

     

32MHz

0

32 MHz Trace Port clock (TRACECLK = 16 MHz)

     

16MHz

1

16 MHz Trace Port clock (TRACECLK = 8 MHz)

     

8MHz

2

8 MHz Trace Port clock (TRACECLK = 4 MHz)

     

4MHz

3

4 MHz Trace Port clock (TRACECLK = 2 MHz)