The ARM® Cortex®-M33 processor has a 32-bit instruction set (Thumb®-2 technology) that implements a superset of 16 and 32-bit instructions to maximize code density and performance.
This processor implements several features that enable energy-efficient arithmetic and high-performance signal processing, including:
The ARM® Cortex Microcontroller Software Interface Standard (CMSIS) hardware abstraction layer for the ARM® Cortex processor series is implemented and available for the M33 CPU.
Real-time execution is highly deterministic in thread mode, to and from sleep modes, and when handling events at configurable priority levels via the nested vectored interrupt controller (NVIC).
Executing code from internal or external flash will have a wait state penalty. The instruction cache can be enabled to minimize flash wait states when fetching instructions. For more information on cache, see Cache. The section Electrical specification shows CPU performance parameters including the wait states in different modes, CPU current and efficiency, and processing power and efficiency based on the CoreMark® benchmark.
The floating-point unit (FPU) may generate exceptions when used due to e.g. overflow or underflow, which in turn will trigger the FPU interrupt.
See Instantiation for more information about which exception number (peripheral ID) is triggered by an FPU exception.
The FPU is not affected by any security configuration. Thus, it appears as not present in PERIPHID[n].PERM register located in the SPU — System protection unit.
To clear the IRQ (interrupt request) line when an exception has occurred, the relevant exception bit within the floating-point status and control register (FPSCR) needs to be cleared. For more information about the FPSCR or other FPU registers, see Cortex-M33 Devices Generic User Guide.
The ARM® Cortex®-M33 processor has a number of CPU options and support modules implemented on the device.
| Option / Module | Description | Implemented |
|---|---|---|
| Core options | ||
| NVIC | Nested vectored interrupt controller | |
| PRIORITIES | Priority bits | 3 |
| WIC | Wake-up interrupt controller | NO |
| Endianness | Memory system endianness | Little endian |
| DWT | Data watchpoint and trace | YES |
| Modules | ||
| MPU_NS | Number of non-secure memory protection unit (MPU) regions | 16 |
| MPU_S | Number of secure MPU regions | 16 |
| SAU | Number of security attribution unit (SAU) regions | 0, see SPU for more information about secure regions. |
| FPU | Floating-point unit | YES |
| DSP | Digital signal processing extension | YES |
| ARMv8-M TrustZone® | ARMv8-M security extensions | YES |
| CPIF | Co-processor interface | NO |
| ETM | Embedded trace macrocell | YES |
| ITM | Instrumentation trace macrocell | YES |
| MTB | Micro trace buffer | NO |
| CTI | Cross trigger interface | YES |
| BPU | Breakpoint unit | YES |
| HTM | AMBA™ AHB trace macrocell | NO |
The CPU clock speed is 64 MHz. Current and efficiency data is taken when in System ON and the CPU is executing the CoreMark™ benchmark. It includes power regulator and clock base currents. All other blocks are IDLE.
| Symbol | Description | Min. | Typ. | Max. | Units | ||||
|---|---|---|---|---|---|---|---|---|---|
| WFLASH |
CPU wait states, running from flash, cache disabled |
0 | 4 | ||||||
| WFLASHCACHE |
CPU wait states, running from flash, cache enabled |
0 | 2 | ||||||
| WRAM |
CPU wait states, running from RAM |
0 | |||||||
| CMFLASH |
CoreMark1, running from flash, cache enabled |
243 | CoreMark | ||||||
| CMFLASH/MHz |
CoreMark per MHz, running from flash, cache enabled |
3.79 | CoreMark/MHz | ||||||
| CMFLASH/mA |
CoreMark per mA, running from flash, cache enabled, DC/DC |
110.45 | CoreMark/mA |