This section describes nRF7002 hardware and layout specifications.
The pin assignment figure and tables describe the pinouts for the device. There are also recommendations for how the General-Purpose Input/Output (GPIO) pins should be configured, in addition to any usage restrictions.
Pin | Name | Function | Description |
---|---|---|---|
1 | OTPVDD | Power | |
2 | N.C. | Do not connect | |
3 | N.C. | Do not connect | |
4 | N.C. | Do not connect | |
5 | N.C. | Do not connect | |
6 | N.C. | Do not connect | |
7 | TXRF<1> | RF | |
8 | PAVDD<1> | Power | |
9 | TXRF<0> | RF | |
10 | PAVDD<0> | Power | |
11 | SXLDO | Power | |
12 | PALDO | Power | |
13 | VBAT | Power | |
14 | RFVDD | Power | |
15 | RFBUCKVDD | Power | |
16 | XOLDO | Power | |
17 | XOP | Analog input | 40MHz crystal |
18 | XON | Analog input | 40MHz crystal |
19 | AFELDO | Power | |
20 | AFEVBAT | Power | |
21 | N.C. | Do not connect | |
22 | N.C. | Do not connect | |
23 | N.C. | Do not connect | |
24 | N.C. | Do not connect | |
25 | BUCKVBAT | Power | |
26 | BUCKOUT | Power | DCDC output |
27 | BUCKVSS | Power | DCDC GND |
28 | BUCKVSS | Power | DCDC GND |
29 | BUCKVMID | Power | Voltage reference decoupling pin |
30 | BUCKEN | Digital I/O | PWR IP enable pin |
31 | BUCKVBATS | Power | |
32 | PWRBUCKVDD | Power | |
33 | DIGVDD | Power | |
34 | PWRIOVDD | Power | |
35 | QSPI_CLK |
Digital I/O | QSPI Clock |
36 | QSPI_SS |
Digital I/O | QSPI Slave select |
37 | QSPI_DATA0 |
Digital I/O | QSPI data |
38 | QSPI_DATA1 |
Digital I/O | QSPI data |
39 | QSPI_DATA2 | Digital I/O | QSPI data |
40 | QSPI_DATA3 | Digital I/O | QSPI data |
41 | COEX_STATUS0 | Digital I/O | Coex interface |
42 | COEX_REQ | Digital I/O | Coex interface |
43 | COEX_GRANT | Digital I/O | Coex interface |
44 | SW_CTRL0 | Digital I/O | External switch control |
45 | SW_CTRL1 | Digital I/O | External switch control |
46 | HOST_IRQ | Digital I/O | Host processor interrupt request |
47 | VSS | Power | |
48 | IOVDD | Power | |
Die pad | VSS | Power | Ground pad. Exposed die pad must be connected to ground (VSS) for proper device operation. |
Dimensions in millimeters for the QFN 6 x 6 mm package.
A | A1 | A2 | b | D | E | D2 | E2 | e | K | L | |
---|---|---|---|---|---|---|---|---|---|---|---|
Min. | 0.8 | 0.15 | 5.9 | 5.9 | 0.2 | 0.2 | |||||
Nom. | 0.85 | 0.035 | 0.65 | 0.2 | 6 | 6 | 4.6 | 4.6 | 0.4 | ||
Max. | 0.9 | 0.05 | 0.25 | 6.1 | 6.1 |
To ensure good RF performance when designing Printed Circuit Board (PCB)s, it is highly recommended to use the PCB layouts and component values provided by Nordic Semiconductor.
Circuit configuration, showing the schematic and Bill of Materials (BOM) table for nRF7002.
Designator | Value | Description | Note |
---|---|---|---|
U1 | nRF7002 | Wi-Fi® 6 Dual Band companion chip | |
U2 | 2.4 / 5 GHz | WLAN Dual Band Diplexer | |
X1 | 40 MHz | Crystal SMD 1612, 40MHz, Cl=8pF | ESR max 100 ohm |
L1 | 3.3µH | Inductor, 1A, ±20%, 200mOhm | |
C1, C2, C6, C11 | 4.7µF | Capacitor, Ceramic, 4.7µF 25V X6S 0603,±10% |
Place C1 close to BUCKVBAT pin Place C2 close to L1 Place C11 close to PALDO pin |
C3 | 0.22uF | Capacitor, Ceramic, 0.22µF 10V X5R 0201, ±10% |
Place C3 close to RFBUCKVDD pin |
C4, C14 | 0.47uF | Capacitor, Ceramic, 0.47µF 6.3V X5R 0201,±10% |
Place C4 close to PWRBUCKVDD pin |
C5 | 1.0µF | Capacitor, Ceramic, 1.0µF 35V X5R 0402,±10% | |
C7, C18 | 2.2µF | Capacitor, Ceramic, 2.2µF 16V X7S 0603,±10% |
Place C7 close to BUCKVBATS pin |
C8 | 10nF | Capacitor, Ceramic, 10nF 16V X7R 0201,±10% | |
C9 | 2.2µF | Capacitor, Ceramic, 2.2µF 25V X5R 0201,±10% | |
C10 | 1.0µF | Capacitor, Ceramic, 1.0µF 16V X6S 0402,±10% | |
C12 | 100nF | Capacitor, Ceramic, 100nF 16V X7S 0201,±10% |
Place C12 close to PAVDD0 pin |
C13 | 22nF | Capacitor, Ceramic, 22nF 10V X5R 0201,±10% | |
C15, C17 | 2.2µF | Capacitor, Ceramic, 2.2µF 10V X5R 0201,±10% | |
C16 | 1.0µF | Capacitor, Ceramic, 1.0µF 10V X7S 0402,±10% |
The various supplies and BUCKEN need to be sequenced in order with delay requirements.
The power up sequence and requirements are:
PWRIOVDD is an internally generated supply, used for supplying OTPVDD through an external connection. It cannot be used for anything else. This supply is automatically controlled in the device.
The power-down sequence and requirements are:
There are no specific timing delay requirements as long as the sequence is correct.
There are two options (high voltage and normal voltage) for connecting nRF7002 to an nRF5340 host, supporting dynamic powerup/powerdown of the nRF7002. This dynamic control utilises an external switch to control the IOVDD supply.
The following figure shows the recommended connection between nRF7002 and the host Microcontroller Unit (MCU) (nRF5340).
Both nRF5340 (used in high voltage mode) and nRF7002 can be supplied from a single 3.6 V supply.
nRF5340 can provide a 1.8 V supply used for the IO supply on nRF7002. An external switch is used to disconnect IOVDD on nRF7002 when not in use. The control of the switch is handled by the Wi-Fi driver on nRF5340.
The nRF7002 can be connected to the nRF5340 host either with a Quad Serial Peripheral Interface (QSPI) or a Serial Peripheral Interface (SPI). QSPI will normally be the preferred option, but in cases where QSPI on the host is used for other purposes SPI can be used.
The following figure shows the connection using QSPI between nRF7002 and the host MCU (nRF5340).
The following figure shows the connections when using SPI between nRF7002 and nRF5340.
The PCB layout shown below is a reference layout for the QFN package.