Hardware and layout

This section describes nRF7002 hardware and layout specifications.

Pin assignments

The pin assignment figure and tables describe the pinouts for the device. There are also recommendations for how the General-Purpose Input/Output (GPIO) pins should be configured, in addition to any usage restrictions.

Figure 1. Pin assignments
Pin assignments
Table 1. Pin assignments
Pin Name Function Description
1 OTPVDD Power  
2 N.C.   Do not connect
3 N.C.   Do not connect
4 N.C.   Do not connect
5 N.C.   Do not connect
6 N.C.   Do not connect
7 TXRF<1> RF 5 GHz
8 PAVDD<1> Power  
9 TXRF<0> RF 2.4 GHz
10 PAVDD<0> Power  
11 SXLDO Power  
12 PALDO Power  
13 VBAT Power  
14 RFVDD Power  
15 RFBUCKVDD Power  
16 XOLDO Power  
17 XOP Analog input 40 MHz crystal (or TCXO output if using an external TCXO)
18 XON Analog input 40 MHz crystal (or N.C. if using an external TCXO)
19 AFELDO Power  
20 AFEVBAT Power  
21 N.C.   Do not connect
22 N.C.   Do not connect
23 N.C.   Do not connect
24 N.C.   Do not connect
25 BUCKVBAT Power  
26 BUCKOUT Power DCDC output
29 BUCKVMID Power Voltage reference decoupling pin
30 BUCKEN Digital I/O PWR IP enable pin
31 BUCKVBATS Power  
33 DIGVDD Power  
34 PWRIOVDD Power  


Digital I/O QSPI Clock

SPI Clock



Digital I/O QSPI Slave select

SPI Slave select



Digital I/O QSPI data

SPI data



Digital I/O QSPI data

SPI data

39 QSPI_DATA2 Digital I/O QSPI data
40 QSPI_DATA3 Digital I/O QSPI data
41 COEX_STATUS0 Digital I/O Coex interface
42 COEX_REQ Digital I/O Coex interface
43 COEX_GRANT Digital I/O Coex interface
44 SW_CTRL0 Digital I/O External switch control
45 SW_CTRL1 Digital I/O External switch control
46 HOST_IRQ Digital I/O Host processor interrupt request
47 VSS Power  
48 IOVDD Power  
49 (Die pad) VSS Power Ground pad. Exposed die pad must be connected to ground (VSS) for proper device operation.

Mechanical specifications

Dimensions in millimeters for the QFN 6 x 6 mm package.

Table 2. Package dimensions in millimeters
  A A1 A2 b D E D2 E2 e K L
Min. 0.8     0.15 5.9 5.9       0.2 0.35
Nom. 0.85 0.035 0.65 0.2 6 6 4.6 4.6 0.4   0.4
Max. 0.9 0.05   0.25 6.1 6.1         0.45

Reference circuitry

To ensure good RF performance when designing Printed Circuit Board (PCB)s, it is highly recommended to use the PCB layouts and component values provided by Nordic Semiconductor.

Reference schematic

Circuit configuration, showing the schematic and Bill of Materials (BOM) table for nRF7002.

Figure 2. nRF7002 reference schematic
nRF7002 reference schematic
Table 3. BOM for nRF7002
Designator Value Description Note
U1 nRF7002 Wi-Fi® 6 Dual Band companion chip  
U2 2.4 / 5 GHz WLAN Dual Band Diplexer  
X1 40 MHz Crystal SMD 1612, 40 MHz, Cl=8 pF ESR max 100 Ω
L1 3.3 µH Inductor, 1 A, ±20%, 200 mΩ  
C1, C2, C6, C11 4.7 µF Capacitor, Ceramic, 4.7 µF 25 V X6S 0603, ±10%

Place C1 close to BUCKVBAT pin

Place C2 close to L1

Place C11 close to PALDO pin

C3 0.22 uF Capacitor, Ceramic, 0.22 µF 10 V X5R 0201, ±10%

Place C3 close to RFBUCKVDD pin

C4, C14 0.47 uF Capacitor, Ceramic, 0.47 µF 6.3 V X5R 0201, ±10%

Place C4 close to PWRBUCKVDD pin

C5 1.0 µF Capacitor, Ceramic, 1.0 µF 35 V X5R 0402, ±10%  
C7, C18 2.2 µF Capacitor, Ceramic, 2.2 µF 16 V X7S 0603, ±10%

Place C7 close to BUCKVBATS pin

C8 10 nF Capacitor, Ceramic, 10 nF 16 V X7R 0201, ±10%  
C9 2.2 µF Capacitor, Ceramic, 2.2 µF 25 V X5R 0402, ±10%  
C10 1.0 µF Capacitor, Ceramic, 1.0 µF 16 V X6S 0402, ±10%  
C12 100 nF Capacitor, Ceramic, 100 nF 16 V X7S 0201, ±10%

Place C12 close to PAVDD0 pin

C13 22 nF Capacitor, Ceramic, 22 nF 10 V X5R 0201, ±10%  
C15 2.2 µF Capacitor, Ceramic, 2.2 µF 10 V X5R 0201, ±10%  
C16 1.0 µF Capacitor, Ceramic, 1.0 µF 10 V X7S 0402, ±10%  
C17 100 nF Capacitor, Ceramic, 100 nF 16 V X7S 0201, ±10%  

Supply sequencing requirements

The various supplies and BUCKEN need to be sequenced in order with delay requirements.

The power up sequence and requirements are:

  • Wait ≥ 6 ms
  • Assert BUCKEN
  • Wait ≥ 1 ms
  • Supply IOVDD

PWRIOVDD is an internally generated supply, used for supplying OTPVDD through an external connection. It cannot be used for anything else. This supply is automatically controlled in the device.

The power-down sequence and requirements are:

  • De-assert BUCKEN and power down IOVDD
  • Power down VBAT

There are no specific timing delay requirements as long as the sequence is correct.

Supply system alternatives

nRF7002 can be powered up/down from a host dynamically. This dynamic control uses the BUCKEN pin and an external switch to control the IOVDD supply. Both the BUCKEN pin and the external switch control are driven from a GPIO on the host, controlled by the Wi-Fi driver.

There are two options (high voltage and normal voltage) for connecting nRF7002 to an nRF5340 host, supporting dynamic powerup/powerdown of the nRF7002. This dynamic control utilises an external switch to control the IOVDD supply.

The following figure shows the recommended connection between nRF7002 and the host Microcontroller Unit (MCU) (nRF5340).

Figure 3. Supply system - high voltage mode
Supply system - high voltage mode

Both nRF5340 (used in high voltage mode) and nRF7002 can be supplied from a single 3.6 V supply.

nRF5340 can provide a 1.8 V supply used for the IO supply on nRF7002. An external switch is used to disconnect IOVDD on nRF7002 when not in use. The control of the switch is handled by the Wi-Fi driver on nRF5340.

Figure 4. Supply system - normal voltage mode
Supply system - normal voltage mode

QSPI/SPI connections

The nRF7002 can be connected to the nRF5340 host either with a Quad Serial Peripheral Interface (QSPI) or a Serial Peripheral Interface (SPI). QSPI is normally the preferred option, but in cases where QSPI on the host is used for other purposes SPI can be used.

The following figure shows the connection using QSPI between nRF7002 and the host MCU (nRF5340).

Figure 5. QSPI connection
QSPI connection

The following figure shows the connections using SPI between nRF7002 and nRF5340.

Figure 6. SPI connection
SPI interface connection

TCXO connection

It is possible to use an external TCXO instead of a crystal.

This option does not require production line trimming, but it will draw more current and hence significantly degrade sleep performance. The TCXO should be disabled when in Shutdown mode to reduce current consumption. It is not possible to dynamically control the TCXO when transitioning between Sleep and Active states. The TCXO should have a typical clipped sine wave output of 0.4 V peak (maximum 0.6 V peak) and be connected through a series capacitor (typically 10 nF).

PCB layout example

The PCB layout in this section is a reference layout for the QFN package.

It is highly recommended to use the layout example as presented with the following boundary clarifications:
  • Keep the antenna connection short.
  • Connect VBAT supply to component C6 in the bottom layer.
  • Connect IOVDD supply to component C18 in the bottom layer.
Figure 7. Top silk layer
Top silk layer
Figure 8. Top layer
Top layer
Figure 9. Mid layer 1
Mid layer 1
Figure 10. Mid layer 2
Mid layer 2
Figure 11. Bottom layer
Bottom layer