nRF7002 includes a 128 x 32-bit One Time Programmable (OTP) memory. This memory is partitioned into two regions, a factory programmed region and a customer programmed region, each containing 64 x 32-bit locations.
The factory programmed region contains information related to production and trim values. The customer programmed region contains:
Quad Serial Peripheral Interface (QSPI) encryption is optional. This is enabled at runtime through a QSPI command. If this feature is not required, the OTP memory locations can remain unprogrammed. For security reasons, the encryption key cannot be read once programmed.
The MAC address fields in the OTP memory are accessed by firmware when powering up the device and presented to the host through an SPI/QSPI-based event as part of the boot phase. The host driver is responsible for configuring the MAC addresses as part of device configuration. As such, the MAC addresses stored in OTP memory can be overwritten by the host. Using this mechanism, the MAC addresses in the OTP memory can remain unprogrammed if an alternate host side storage is used.
The only module level calibration coefficient is the crystal oscillator trim. This is required to minimize the frequency offset resulting from the external 40 MHz crystal. See Device Commissioning and Characterization for information related to calibration.
Although the OTP memory is one time programmable, any bit still in a 1 state can be reprogrammed into a 0 state. To avoid deliberate or inadvertent modification of the OTP memory data, a protection mechanism is provided. The protection registers initially need to be programmed to 0x50FA50FA in order to activate programming of the remaining locations. Once OTP memory programming is complete, the protection registers should be programmed to 0x00000000, at which point the OTP memory can never be modified.
In addition to the logical protection mechanism described above, a programming voltage needs to be applied to the OTPVDD pin in order to enable programming. The programming voltage is 2.5 V, while for reads it is 1.8 V. To coordinate the OTPVDD supply voltage with read and write operations, it is recommended to drive this supply from the POWERIOVDD output pin on nRF7002. This also ensures there will be no leakage associated with the OTP memory across sleep cycles, where the digital supply rail is removed.
The OTP memory is indirectly mapped, and as such read and writes are achieved using address, data, and mode registers. The OTP memory programming utility implements this programming, along with appropriate control of the OTPVDD supply through the POWERIOVDD output.