REGULATORS - Regulator control

All system components are powered from the on-chip voltage regulators. These regulators are responsible for converting the voltage supplied on the VDD or VDDH pins to adequate voltages to be used internally.

The available regulators can be configured in multiple ways to accomodate different input voltage ranges. Some modes support sourcing power to external circuitry. The voltage modes that are supported by nRF5340 are listed in the following table.

Table 1. Supported voltage modes
Voltage mode Input voltage range Output voltage range
Normal voltage mode 1.7 V - 3.6 V -
High voltage mode 2.5 V - 5.5 V 1.8 V - 3.3 V

For an overview on the available regulators, see Power supply modes and regulators.

Normal voltage mode - detailed setup

Normal voltage mode uses the main regulator (VREGMAIN) and the radio regulator (VREGRADIO).

The VREGMAIN and VREGRADIO regulators operate in LDO mode by default. DC/DC mode can be enabled independently for each regulator using VREGMAIN.DCDCEN ( Retained ) and VREGRADIO.DCDCEN ( Retained ) respectively.

When configured as shown in the following figure, the nRF5340 enters normal voltage mode. Here both regulators are in DC/DC mode. An external LC filter is required for each regulator in DC/DC mode. If a regulator is only to be used in LDO mode, the inductor for this regulator is not needed. In this mode, the VDDH pin must be connected to VDD, even if the high voltage regulator (VREGH) is not in use.

Figure 1. Normal voltage mode
Normal voltage mode setup with regulators in DC/DC mode

The advantage of using a regulator in DC/DC mode is that the overall power consumption is reduced. This is because the regulator in DC/DC mode has a higher efficiency than in LDO mode. Regulator efficiency in DC/DC mode varies depending on the supply voltage and the current drawn from the regulators.

High voltage mode - detailed setup

High voltage mode uses the main regulator (VREGMAIN), the high voltage regulator (VREGH), and the radio regulator (VREGRADIO).

All regulators operate in LDO mode by default. DC/DC mode can be enabled independently for each regulator using VREGMAIN.DCDCEN ( Retained ), VREGH.DCDCEN ( Retained ), and VREGRADIO.DCDCEN ( Retained ).

When configured as shown in the following figure, the nRF5340 enters high voltage mode. Here all three regulators are in DC/DC mode. An external LC filter is required for each of the regulators in DC/DC mode. If a regulator is only to be used in LDO mode, the inductor for this regulator is not needed.

Figure 2. High voltage mode
High voltage mode setup with regulators in DC/DC mode

The advantage of using a regulator in DC/DC mode is that the overall power consumption is reduced. This is because the regulator in DC/DC mode has higher efficiency than when in LDO mode. Regulator efficiency in DC/DC mode varies depending on the supply voltage and the current drawn from the regulators.

External circuitry supply

In high voltage mode, the output from VREGH can be used to supply external circuitry from the VDD pin.

As illustrated in High voltage mode - detailed setup, external circuitry can be powered from the VDD pin once it is enabled in the register EXTSUPPLY.

The VDD output voltage is programmed in the register VREGHVOUT.

The supported output voltage range depends on the supply voltage provided to the VDDH pin. The difference between voltage supplied on the VDDH pin and the voltage output on the VDD pin is defined by the VREGH,DROP parameter in Regulator specifications, VREGH stage.

Supplying power to external circuitry is allowed in both System OFF and System ON mode.

Note: The maximum allowed current drawn by external circuitry is dependent on the total internal current draw. The maximum current that can be drawn externally from REGH is defined in Regulator specifications, VREGH stage).

GPIO levels

The GPIO high reference voltage depends on the regulator voltage mode.

In normal voltage mode, the GPIO high level equals the voltage supplied to the VDD pin. In high voltage mode, it equals the level specified in the VREGHVOUT register.

Registers

Table 2. Instances
Base address Domain Peripheral Instance Secure mapping DMA security Description Configuration

0x50004000
0x40004000

APPLICATION REGULATORS

REGULATORS : S
REGULATORS : NS

US

NA

Regulator configuration

   
Table 3. Register overview
Register Offset Security Description
MAINREGSTATUS 0x428  

Main supply status

Retained

SYSTEMOFF 0x500  

System OFF register

 
POFCON 0x510  

Power-fail comparator configuration

Retained

VREGMAIN.DCDCEN 0x704  

DC/DC enable register for VREGMAIN

Retained

VREGRADIO.DCDCEN 0x904  

DC/DC enable register for VREGRADIO

Retained

VREGH.DCDCEN 0xB00  

DC/DC enable register for VREGH

Retained

MAINREGSTATUS ( Retained )

Address offset: 0x428

This register is a retained register

Main supply status

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                              

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A R

VREGH

   

VREGH status

     

Inactive

0

Normal voltage mode. Voltage supplied on VDD and VDDH.

     

Active

1

High voltage mode. Voltage supplied on VDDH.

SYSTEMOFF

Address offset: 0x500

System OFF register

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                              

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A W

SYSTEMOFF

   

Enable System OFF mode

     

Enter

1

Enable System OFF mode

POFCON ( Retained )

Address offset: 0x510

This register is a retained register

Power-fail comparator configuration

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                        

D

D

D

D

   

B

B

B

B

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

POF

   

Enable or disable power-fail comparator

     

Disabled

0

Disable

     

Enabled

1

Enable

B RW

THRESHOLD

   

Power-fail comparator threshold setting

     

V19

6

Set threshold to 1.9 V

     

V20

7

Set threshold to 2.0 V

     

V21

8

Set threshold to 2.1 V

     

V22

9

Set threshold to 2.2 V

     

V23

10

Set threshold to 2.3 V

     

V24

11

Set threshold to 2.4 V

     

V25

12

Set threshold to 2.5 V

     

V26

13

Set threshold to 2.6 V

     

V27

14

Set threshold to 2.7 V

     

V28

15

Set threshold to 2.8 V

D RW

THRESHOLDVDDH

   

Power-fail comparator threshold setting for voltage supply on VDDH

     

V27

0

Set threshold to 2.7 V

     

V28

1

Set threshold to 2.8 V

     

V29

2

Set threshold to 2.9 V

     

V30

3

Set threshold to 3.0 V

     

V31

4

Set threshold to 3.1 V

     

V32

5

Set threshold to 3.2 V

     

V33

6

Set threshold to 3.3 V

     

V34

7

Set threshold to 3.4 V

     

V35

8

Set threshold to 3.5 V

     

V36

9

Set threshold to 3.6 V

     

V37

10

Set threshold to 3.7 V

     

V38

11

Set threshold to 3.8 V

     

V39

12

Set threshold to 3.9 V

     

V40

13

Set threshold to 4.0 V

     

V41

14

Set threshold to 4.1 V

     

V42

15

Set threshold to 4.2 V

VREGMAIN.DCDCEN ( Retained )

Address offset: 0x704

This register is a retained register

DC/DC enable register for VREGMAIN

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                              

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

DCDCEN

   

Enable or disable DC/DC converter

     

Disabled

0

Disable

     

Enabled

1

Enable

VREGRADIO.DCDCEN ( Retained )

Address offset: 0x904

This register is a retained register

DC/DC enable register for VREGRADIO

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                              

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

DCDCEN

   

Enable or disable DC/DC converter

     

Disabled

0

Disable

     

Enabled

1

Enable

VREGH.DCDCEN ( Retained )

Address offset: 0xB00

This register is a retained register

DC/DC enable register for VREGH

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                              

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID Access Field Value ID Value Description
A RW

DCDCEN

   

Enable or disable DC/DC converter

     

Disabled

0

Disable

     

Enabled

1

Enable

Electrical specification

Regulator startup times

Symbol Description Min. Typ. Max. Units
tPOR

Time in power-on reset after VDD reaches 1.7 V for all supply voltages and temperatures. Dependent on supply rise time. 1

.. .. ..  
tPOR,10us

VDD rise time 10 µs

.. .. .. ms
tPOR,10ms

VDD rise time 10 ms

.. .. .. ms
tPOR,60ms

VDD rise time 60 ms

.. .. .. ms
tRISE,VREGHOUT

VREGH output (VDD) rise time after VDDH reaches minimum VDDH supply voltage

.. .. ..  
tRISE,VREGHOUT,10us

VDDH rise time 10 µs

.. .. .. ms
tRISE,VREGHOUT,10ms

VDDH rise time 10 ms

.. .. .. ms
tRISE,VREGHOUT,50ms

VDDH rise time 50 ms

.. .. .. ms
tPINR

If a GPIO pin is configured as reset, the maximum time taken to pull up the pin and release reset after power on reset. Dependent on the pin capacitive load (C).2:t=5RC, R=13 kΩ

.. .. ..  
tPINR,500nF

C = 500 nF

.. .. .. ms
tPINR,10uF

C = 10 µF

.. .. .. ms

Application core startup times

Symbol Description Min. Typ. Max. Units
tR2ON

Time from reset to ON (CPU execute)

.. .. ..  
tR2ON,NOTCONF

If reset pin not configured

.. .. .. ms
tR2ON,CONF

If reset pin configured

.. .. .. ms
tOFF2ON,NM

Time from OFF to CPU execute when in normal voltage mode (supply on VDD)

.. .. .. µs
tOFF2ON,LDO,HV

Time from OFF to CPU execute when in high voltage mode (supply on VDDH) and VREGH using LDO regulator

.. .. .. µs
tOFF2ON,DCDC,HV

Time from OFF to CPU execute when in high voltage mode (supply on VDDH) and VREGH using DC/DC regulator

.. .. .. µs
tIDLE2CPU

Time from IDLE to CPU execute

.. .. .. µs
tEVTSET,CL1

Time from HW event to PPI event in constant latency System ON mode

.. .. .. µs
tEVTSET,CL0

Time from HW event to PPI event in low power System ON mode

.. .. .. µs

Network core startup times

Symbol Description Min. Typ. Max. Units
tNET,EVTSET,CL1

Time from HW event to PPI event in constant latency System ON mode

.. .. .. µs
tNET,EVTSET,CL0

Time from HW event to PPI event in low power System ON mode

.. .. .. µs
tNET,IDLE2CPU

Time from IDLE to CPU execute

.. .. .. µs
tFO2ON,NET64

Time for network core from OFF to CPU execute after NETWORK.FORCEOFF is released

.. .. .. µs

Power-fail comparator

Symbol Description Min. Typ. Max. Units
VPOF,NV

Nominal power level warning thresholds (falling supply voltage) in normal voltage mode (supply on VDD). Levels are configurable between min. and max. in increments of 100 mV.

.. .. .. V
VPOF,HV

Nominal power level warning thresholds (falling supply voltage) in high voltage mode (supply on VDDH). Levels are configurable between min. and max. in increments of 100 mV.

.. .. .. V
VPOF,LV

Nominal power level warning thresholds (falling supply voltage) in low voltage mode (supply on VDDL). Levels are configurable between min. and max. in increments of 100 mV.

.. .. .. V
VPOFTOL

Threshold voltage tolerance (applies in both normal voltage mode and high voltage mode)

.. .. .. %
VPOFHYST

Threshold voltage hysteresis (applies in both normal voltage mode and high voltage mode)

.. .. .. mV
VBOR,OFF

Brownout reset voltage range System OFF mode. Brownout only applies to the voltage on VDD.

.. .. .. V
VBOR,ON

Brownout reset voltage range System ON mode. Brownout only applies to the voltage on VDD.

.. .. .. V

Regulator specifications, VREGH stage

Symbol Description Min. Typ. Max. Units
VDDOUT

VDD output voltage.

.. .. .. V
IEXT,OFF

External current draw3 allowed in High voltage mode (supply on VDDH) during System OFF.

.. .. .. mA
IEXT,LOW

External current draw3 allowed in High voltage mode (supply on VDDH) when radio output power is higher than TBD dBm.

.. .. .. mA
IEXT,HIGH

External current draw3 allowed in High voltage mode (supply on VDDH) when radio output power is lower than or equal to TDB dBm.

.. .. .. mA
VREGH,DROP

Minimum voltage drop in REGH (difference between voltage supplied on VDDH pin and voltage output on VDD pin).

.. .. .. V
1 A step increase in supply voltage of 300 mV or more, with rise time of 300 ms or less, within the valid supply range, may result in a system reset.
2 To decrease maximum time a device could hold in reset, a strong external pullup resistor can be used.
3 External current draw is defined as the sum of all GPIO currents and the current being drawn from VDD.

This document was last updated on
2019-12-09.
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