CPU

The Arm® Cortex®-M33 processor has a 32-bit instruction set (Thumb®-2 technology) that implements a superset of 16- and 32-bit instructions to maximize code density and performance.

This processor implements several features that enable energy-efficient arithmetic and high-performance signal processing including:

The Arm Cortex Microcontroller Software Interface Standard (CMSIS) is implemented and available for the application processor.

Real-time execution is highly deterministic in thread mode, to and from sleep modes, and when handling events at configurable priority levels via the Nested Vectored Interrupt Controller (NVIC).

Executing code from internal or external flash will have a wait state penalty. The instruction cache can be enabled to minimize flash wait states when fetching instructions. For more information on cache, see Cache. CPU performance parameters including wait states for different configurations, CPU current consumpion and efficiency, and processing power and efficiency based on the CoreMark® benchmark can be found in .

Floating point interrupt

The floating point unit (FPU) may generate exceptions, for example, due to overflow or underflow. These exceptions may trigger interrupts when enabled in the FPU peripheral. For more information, see FPU - Floating point unit (FPU) exceptions.

Electrical specification

CPU performance

Symbol Description Min. Typ. Max. Units
WFLASH

CPU wait states, running from flash, cache disabled

.. .. ..  
WFLASHCACHE

CPU wait states, running from flash, cache enabled

.. .. ..  
WRAM

CPU wait states, running from RAM

.. .. ..  
CMFLASH

CoreMark1, running from flash, cache enabled, HFXO128M

510 CoreMark
CMFLASH/MHz

CoreMark per MHz, running from flash, cache enabled, HFXO128M

3.9 CoreMark/MHz
CMFLASH/mA

CoreMark per mA, running from flash, cache enabled, DCDC 3V, HFXO128M

65 CoreMark/mA
CMFLASH

CoreMark2, running from flash, cache enabled, HFXO64M

255 CoreMark
CMFLASH/MHz

CoreMark per MHz, running from flash, cache enabled, HFXO64M

3.9 CoreMark/MHz
CMFLASH/mA

CoreMark per mA, running from flash, cache enabled, DCDC 3V, HFXO64M

76 CoreMark/mA

CPU and support module configuration

The Arm Cortex®-M33 processor has a number of CPU options and support modules implemented on the device.

Option/Module Description Implemented
Core options
PRIORITIES Priority bits 3
WIC Wakeup Interrupt Controller NO
Endianness Memory system endianness Little endian
DWT Data Watchpoint and Trace YES
Modules
MPU_NS Number of non-secure MPU regions 8
MPU_S Number of secure MPU regions 8
SAU Number of SAU regions 0

See SPU for more information about secure regions.

FPU Floating-point unit YES
DSP Digital Signal Processing Extension YES
Arm TrustZone® for Armv8-M ARMv8-M Security Extensions YES
CPIF Coprocessor interface NO
ETM Embedded Trace Macrocell YES
ITM Instrumentation Trace Macrocell YES
MTB Micro Trace Buffer NO
CTI Cross Trigger Interface YES
BPU Breakpoint Unit YES
HTM AHB Trace Macrocell NO
1 Using ARMCLANG compiler
2 Using ARMCLANG compiler

This document was last updated on
2019-12-09.
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