AHB multilayer

AHB multilayer enables parallel access paths between multiple masters and slaves in a system. Access is resolved using priorities.

Each bus master is connected to a slave device through one or more interconnection matrixes. The bus masters are assigned priorities that are used to resolve access when two (or more) bus masters request access to the same slave device. The following applies when assigning priorities:

Some peripherals, like I2S, do not have a safe stalling mechanism (not able to pause incoming data and no internal data buffering). Being a low priority bus master might cause loss of data for such peripherals upon bus contention. To avoid AHB bus contention when using multiple bus masters, apply one of the following guidelines:

AHB multilayer priorities

Each master connected to the AHB multilayer is assigned a default natural priority.

Table 1. AHB bus masters
Bus master name Natural relative priority In/Out
CPU Highest priority I/O
Network core   I/O
I2S   I/O
PDM   I
UARTE0, SPIM0, SPIS0, TWIM0, TWIS0   I/O
UARTE1, SPIM1, SPIS1, TWIM1, TWIS1   I/O
UARTE2, SPIM2, SPIS2, TWIM2, TWIS2   I/O
UARTE3, SPIM3, SPIS3, TWIM3, TWIS3   I/O
SAADC   I
PWM0   O
PWM1   O
PWM2   O
PWM3   O
SPIM4   I/O
NFCT   I/O
CC312   I/O
QSPI Lowest priority I/O

This document was last updated on
2019-12-09.
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