Memory

The network core contains flash memory and RAM that can be used for code and data storage.

The following figure shows how the CPU and peripherals with EasyDMA can access RAM via the AHB multilayer interconnect.

The network core can access application core resources (flash, RAM, and peripherals) when granted permission through the application's DCNF and SPU settings. A small portion of the application core RAM is dedicated to the exchange of messages between the application and network cores.

Figure 1. Memory layout
Memory layout

Peripheral instantiation

The following table describes the abbreviations used in the Instance, Secure mapping, and DMA security columns of the instantiation table.

Table 1. Instantiation table abbreviations
Abbreviation Description
NS Non-secure - Peripheral is always accessible as a Non-Secure peripheral
S Secure - Peripheral is always accessible as a Secure peripheral
US User Selectable - A Secure or Non-secure attribute for the peripheral is defined in the SPU
SPLIT Both Secure and Non-secure - The same resource is shared by both secure and non-secure code
NA Not Applicable - Peripheral has no DMA capability
NSA NoSeparateAttribute - Peripheral with DMA and DMA transfer has the same security attribute as assigned to the peripheral
SA SeparateAttribute - Peripheral with DMA and DMA transfers can have a different security attribute than the one assigned to the peripheral

The Secure mapping column in the following table defines configuration capabilities for the Arm® TrustZone® for Armv8-M secure attribute. The DMA security column describes the DMA capabilities of the peripheral.

Instantiation

Table 2. Instantiation table
ID Base address Peripheral Instance Secure mapping DMA security Description
0 0x41000000 DCNF DCNF NS NA

Domain configuration

 
4 0x41004000 VREQCTRL VREQCTRL NS NA

Voltage request control

 
5 0x41005000 CLOCK CLOCK NS NA

Clock control

 
5 0x41005000 POWER POWER NS NA

Power control

 
5 0x41005000 RESET RESET NS NA

Reset status

 
6 0x41006000 CTRLAPPERI CTRLAP NS NA

Control access port CPU side

 
8 0x41008000 RADIO RADIO NS NA

2.4 GHz radio

 
9 0x41009000 RNG RNG NS NA

Random number generator

 
10 0x4100A000 GPIOTE GPIOTE NS NA

GPIO tasks and events

 
11 0x4100B000 WDT WDT NS NA

Watchdog timer

 
12 0x4100C000 TIMER TIMER0 NS NA

Timer 0

 
13 0x4100D000 ECB ECB NS NA

AES ECB mode encryption

 
14 0x4100E000 AAR AAR NS NA

Accelerated address resolver

 
14 0x4100E000 CCM CCM NS NA

AES CCM mode encryption

 
15 0x4100F000 DPPIC DPPIC NS NA

DPPI controller

 
16 0x41010000 TEMP TEMP NS NA

Temperature sensor

 
17 0x41011000 RTC RTC0 NS NA

Real-time counter 0

 
18 0x41012000 IPC IPC NS NA

Interprocessor communication

 
19 0x41013000 SPIM SPIM0 NS NA

SPI master 0

 
19 0x41013000 SPIS SPIS0 NS NA

SPI slave 0

 
19 0x41013000 TWIM TWIM0 NS NA

Two-wire interface master 0

 
19 0x41013000 TWIS TWIS0 NS NA

Two-wire interface slave 0

 
19 0x41013000 UARTE UARTE0 NS NA

Universal asynchronous receiver/transmitter

 
20 0x41014000 EGU EGU0 NS NA

Event generator unit 0

 
22 0x41016000 RTC RTC1 NS NA

Real-time counter 1

 
24 0x41018000 TIMER TIMER1 NS NA

Timer 1

 
25 0x41019000 TIMER TIMER2 NS NA

Timer 2

 
26 0x4101A000 SWI SWI0 NS NA

Software interrupt 0

 
27 0x4101B000 SWI SWI1 NS NA

Software interrupt 1

 
28 0x4101C000 SWI SWI2 NS NA

Software interrupt 2

 
29 0x4101D000 SWI SWI3 NS NA

Software interrupt 3

 
128 0x41080000 ACL ACL NS NA

Access control lists

 
128 0x41080000 NVMC NVMC NS NA

Non-Volatile Memory Controller

 
129 0x41081000 VMC VMC NS NA

Volatile memory controller

 
192 0x418C0500 GPIO P0 NS NA

General purpose input and output

 
192 0x418C0800 GPIO P1 NS NA

General purpose input and output

 
N/A 0x01FF0000 FICR FICR NS NA

Factory information configuration

 
N/A 0x01FF8000 UICR UICR NS NA

User information configuration

 
N/A 0xE0042000 CTI CTI NS NA

Cross-trigger interface

 

This document was last updated on
2019-12-09.
Please send us your feedback about the documentation! For technical questions, visit the Nordic Developer Zone.