CPU

The Arm® Cortex®-M33 processor has a 32-bit instruction set (Thumb®-2 technology) that implements a superset of 16- and 32-bit instructions to maximize code density and performance.

This processor implements several features that enable energy-efficient arithmetic and high-performance signal processing including:

The Arm Cortex Microcontroller Software Interface Standard (CMSIS) is implemented and available for the application processor.

Real-time execution is highly deterministic in thread mode, to and from sleep modes, and when handling events at configurable priority levels via the Nested Vectored Interrupt Controller (NVIC).

Executing code from internal or external flash will have a wait state penalty. The instruction cache can be enabled to minimize flash wait states when fetching instructions. For more information on cache, see NVMC — Non-volatile memory controller. CPU performance parameters including mode wait states, CPU current and efficiency, and processing power and efficiency based on the CoreMark® benchmark can be found in .

Electrical specification

CPU performance

Symbol Description Min. Typ. Max. Units
WFLASH

CPU wait states, running from flash, cache disabled

.. .. ..  
WFLASHCACHE

CPU wait states, running from flash, cache enabled

.. .. ..  
WRAM

CPU wait states, running from RAM

.. .. ..  
CMFLASH

CoreMark1, running from flash, cache enabled

238 CoreMark
CMFLASH/MHz

CoreMark per MHz, running from flash, cache enabled

3.7 CoreMark/MHz
CMFLASH/mA

CoreMark per mA, running from flash, cache enabled, DCDC 3V

101 CoreMark/mA

CPU and support module configuration

The Arm Cortex®-M33 processor has a number of CPU options and support modules implemented on the device.

Option/Module Description Implemented
Core options
PRIORITIES Priority bits 3
WIC Wakeup Interrupt Controller NO
Endianness Memory system endianness Little endian
DWT Data Watchpoint and Trace YES
Modules
MPU_NS Number of non-secure MPU regions 8
MPU_S Number of secure MPU regions 0 (No ARMv8-M Security Extensions)
SAU Number of SAU regions 0 (No Arm TrustZone® for Armv8-M Security Extensions)
FPU Floating-point unit NO
DSP Digital Signal Processing Extension NO
ARMv8-M TrustZone Arm TrustZone® for Armv8-M Security Extensions NO
CPIF Coprocessor interface NO
ETM Embedded Trace Macrocell NO
ITM Instrumentation Trace Macrocell NO
MTB Micro Trace Buffer NO
CTI Cross Trigger Interface YES
BPU Breakpoint Unit YES
HTM AHB Trace Macrocell NO
1 Using ARM compiler

This document was last updated on
2019-12-09.
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