FICR — Factory information configuration registers

Factory information configuration registers (FICR) are pre-programmed in factory and cannot be erased by the user. These registers contain chip-specific information and configuration.

Registers

Table 1. Instances
Base address	Domain	Peripheral	Instance	Secure mapping	DMA security	Description	Configuration
0x01FF0000	NETWORK	FICR	FICR	NS	NA	Factory information configuration

Table 2. Register overview
Register	Offset	Description
INFO.CONFIGID	0x200	Configuration identifier
INFO.DEVICEID[n]	0x204	Device identifier
INFO.PART	0x20C	Part code
INFO.VARIANT	0x210	Part Variant, Hardware version and Production configuration
INFO.PACKAGE	0x214	Package option
INFO.RAM	0x218	RAM variant
INFO.FLASH	0x21C	Flash variant
INFO.CODEPAGESIZE	0x220	Code memory page size in bytes
INFO.CODESIZE	0x224	Code memory size
INFO.DEVICETYPE	0x228	Device type
ER[n]	0x280	Encryption Root, word n
IR[n]	0x290	Identity Root, word n
DEVICEADDRTYPE	0x2A0	Device address type
DEVICEADDR[n]	0x2A4	Device address n
TRIMCNF[n].ADDR	0x300	Address
TRIMCNF[n].DATA	0x304	Data

INFO.CONFIGID

Address offset: 0x200

Configuration identifier

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0xFFFFFFFF				1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	R	HWID										Identification number for the HW

INFO.DEVICEID[n] (n=0..1)

Address offset: 0x204 + (n × 0x4)

Device identifier

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0xFFFFFFFF				1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	R	DEVICEID										64 bit unique device identifier DEVICEID[0] contains the least significant bits of the device identifier. DEVICEID[1] contains the most significant bits of the device identifier.

INFO.PART

Address offset: 0x20C

Part code

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00005340				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	1	0	0	1	1	0	1	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	PART										Part code
			N5340	0x5340								nRF5340
			Unspecified	0xFFFFFFFF								Unspecified

INFO.VARIANT

Address offset: 0x210

Part Variant, Hardware version and Production configuration

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0xFFFFFFFF				1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	R	VARIANT										Part Variant, Hardware version and Production configuration, encoded as ASCII
			QKAA	0x514B4141								QKAA
			CLAA	0x434C4141								CLAA
			Unspecified	0xFFFFFFFF								Unspecified

INFO.PACKAGE

Address offset: 0x214

Package option

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0xFFFFFFFF				1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	R	PACKAGE										Package option
			QK	0x2000								QKxx - 94-pin aQFN
			CL	0x2005								CLxx - WLCSP
			Unspecified	0xFFFFFFFF								Unspecified

INFO.RAM

Address offset: 0x218

RAM variant

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0xFFFFFFFF				1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	R	RAM										RAM variant
			K16	0x10								16 kByte RAM
			K32	0x20								32 kByte RAM
			K64	0x40								64 kByte RAM
			K128	0x80								128 kByte RAM
			K256	0x100								256 kByte RAM
			K512	0x200								512 kByte RAM
			Unspecified	0xFFFFFFFF								Unspecified

INFO.FLASH

Address offset: 0x21C

Flash variant

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0xFFFFFFFF				1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	R	FLASH										Flash variant
			K128	0x80								128 kByte FLASH
			K256	0x100								256 kByte FLASH
			K512	0x200								512 kByte FLASH
			K1024	0x400								1 MByte FLASH
			K2048	0x800								2 MByte FLASH
			Unspecified	0xFFFFFFFF								Unspecified

INFO.CODEPAGESIZE

Address offset: 0x220

Code memory page size in bytes

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000800				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	CODEPAGESIZE										Code memory page size in bytes
			K2048	0x800								2 kByte

INFO.CODESIZE

Address offset: 0x224

Code memory size

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000080				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	CODESIZE										Code memory size in number of pages Total code space is: CODEPAGESIZE * CODESIZE bytes
			P128	128								128 pages

INFO.DEVICETYPE

Address offset: 0x228

Device type

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	DEVICETYPE										Device type
			Die	0x0000000								Device is an physical DIE
			FPGA	0xFFFFFFFF								Device is an FPGA

ER[n] (n=0..3)

Address offset: 0x280 + (n × 0x4)

Encryption Root, word n

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0xFFFFFFFF				1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	R	ER										Encryption Root, word n

IR[n] (n=0..3)

Address offset: 0x290 + (n × 0x4)

Identity Root, word n

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0xFFFFFFFF				1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	R	IR										Identity Root, word n

DEVICEADDRTYPE

Address offset: 0x2A0

Device address type

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0xFFFFFFFF				1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	R	DEVICEADDRTYPE										Device address type
			Public	0								Public address
			Random	1								Random address

DEVICEADDR[n] (n=0..1)

Address offset: 0x2A4 + (n × 0x4)

Device address n

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0xFFFFFFFF				1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	R	DEVICEADDR										48 bit device address DEVICEADDR[0] contains the least significant bits of the device address. DEVICEADDR[1] contains the most significant bits of the device address. Only bits [15:0] of DEVICEADDR[1] are used.

TRIMCNF[n].ADDR (n=0..31)

Address offset: 0x300 + (n × 0x8)

Address

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0xFFFFFFFF				1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	R	Address										Address

TRIMCNF[n].DATA (n=0..31)

Address offset: 0x304 + (n × 0x8)

Data

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0xFFFFFFFF				1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
ID	R/W	Field	Value ID	Value								Description
A	R	Data										Data