CLOCK — Clock control

The clock control system can source the system clocks from a range of internal or external high and low frequency oscillators, and distribute them to peripherals and modules based on their individual requirements. Clock distribution is automated and grouped independently by module to limit current consumption in unused branches of the clock tree.

Each core subsystem has its own clock control system that is responsible for requesting resources from the power and clock subsystem.

Figure 1. Clock control

The power and clock subsystem secures glitch-free switching from one clock source to another. This applies to all clock sources.

Note: Registers INTEN, INTENSET, and INTENCLR are the same registers (at the same address) as the corresponding registers in POWER.

HFCLK controller

Each core has a number of high frequency clock (HFCLK) control instances. Each instance distributes one or more clocks to the core.

The following table lists the core clocks that are available.

Table 1. Core clocks
Core clock	Description
HCLK128M	Scalable 128 MHz CPU clock for the application core
HCLK64M	64 MHz CPU clock for the network core
PCLK192M	Scalable 192 MHz clock for QSPI
PCLK64M	64 MHz peripheral clock
PCLK48M	48 MHz clock for USB
PCLK32M	32 MHz peripheral clock
PCLK16M	16 MHz peripheral clock
PCLK1M	1 MHz peripheral clock
ACLK	11.289 MHz or 12.288 MHz tunable audio peripheral clock

The HFCLK clocks sourced from the power and clock subsystem to the HFCLK control instances are the following:

Table 2. HFCLK clocks for HFCLK control instances
HFCLK clock	Description
HFCLK128M	128 MHz HFCLK clock
HFCLK64M	64 MHz HFCLK clock
HFCLK192M	192 MHz HFCLK clock
HFCLKAUDIO	Audio HFCLK clock

In order to generate the HFCLK clocks, the following HFCLK sources are available:

192 MHz/128 MHz/64 MHz internal oscillator (HFINT)
32 MHz crystal oscillator (HFXO), optionally using built-in capacitors as described in OSCILLATORS — Oscillator control

See Clock control for more information.

CPUs, peripherals, and other system components within a core will automatically request clocks from its corresponding local HFCLK control. The HFCLK control passes the request to the power and clock subsystem and, once the clocks are running, distributes them to the components within the core.

When HFCLK control requests within a core are stopped, the HFCLK control will stop requesting clock from the power and clock subsystem. For example, when the CPU enters sleep or when peripherals have completed their tasks. If there are no HFCLK control requests from any core, the power and clock subsystem will automatically stop the clock.

When the system enters System ON mode, and a HFCLK clock is requested, the relevant HFINT will be used as the HFCLK source. When requests for the clock are stopped, the HFINT will automatically stop.

HFCLK clocks are only available to the HFCLK controllers when the system is in System ON mode.

It is possible to have a HFCLK source running before being started by the relevant clock request (for instance, the HFCLK source is kept running during sleep). This gives shorter start-up time but causes increased power consumption. Starting the HFXO is needed when crystal clock accuracy is required.

The HFCLK source selected in register HFCLKSRC is started by triggering the HFCLKSTART task.

The source for the HFCLK128M/HFCLK64M clocks can be configured at any time (for instance, when the HFCLK has already been started). The content of the HFCLKSRC register only takes effect when the HFCLKSTART task is triggered.

The event HFCLKSTARTED is generated when the HFCLKSTART task is triggered, the oscillator is started, and the frequency is stabilized.

The HFCLK source selected in register HFCLK192MSRC is started by triggering the HFCLK192MSTART task.

The source for the HFCLK192M clock can be configured at any time (for instance, when the HFCLK has already been started). The content of the HFCLK192MSRC register only takes effect when the HFCLK192MSTART task is triggered.

The event HFCLK192MSTARTED is generated when the HFCLK192MSTART task is triggered, the oscillator is started, and the frequency stabilized.

HFCLKAUDIO requires HFXO, so when triggering the HFCLKAUDIOSTART task, this always starts the HFXO.

The event HFCLKAUDIOSTARTED is generated when the HFCLKAUDIOSTART task is triggered, the oscillator is started, and the frequency stabilized.

It is possible to trigger a new START task after one has already been triggered, and before the corresponding STARTED event is generated. In this case, only one STARTED event will be generated, corresponding to the last triggered START task. Triggering a START task after the STARTED event from a previous triggered START taks is generated, will generate a new STARTED event.

Time from a START task to the corresponding STARTED event may differ depending on whether the HFCLK source is already running or in the process of starting. The amount of time before a STARTED event may vary when a different HFCLK source is configured before triggering a new START task.

When the clock control system switches from HFINT source to HFXO source, the HFXO becomes active. The startup time is programmable, enabling the use of different types of crystal oscillators (e.g. standard crystals that may have different startup times). The HFXO startup time is given as the sum of the following:

HFXO power-up time, as specified in 32 MHz crystal oscillator (HFXO).
HFXO count time, as specified in HFXOCNT.

The HFXO must be selected and started in order to do the following:

Use RADIO
- The network domain HFCLKSTART task is used
Enable USBD to respond to USB traffic
- The application domain HFCLK192MSTART is used
Set NFCT to activated state
- The application domain HFCLKSTART task is used
Improve SAADC performance by reducing clock jitter
- The application domain HFCLKSTART task is used

Each HFCLK control can request the HFXO source independently from one another via the corresponding START task. This ensures that each core and peripheral will have access to a high accuracy clock when needed. Core clocks that originate from the same HFCLK clock will also have the same HFCLK source. This means that parts of the core that have not requested the HFXO may get a clock that is more accurate than expected, but not the other way around.

All cores that have requested a HFCLK source to start by triggering a START task must also request it to stop by triggering the corresponding STOP task (see HFCLKSTOP, HFCLK192MSTOP, and HFCLKAUDIOSTOP tasks) before the power and clock subsystem will stop it.

HFCLK source(s) will stop when all corresponding STOP tasks have been triggered and there are no requests for HFCLK clock(s) from the system.

Triggering a HFCLK STOP task is required only if the corresponding HFCLK START task has been triggered before. When a HFCLK START task is triggered, it is possible to trigger again the same HFCLK START task without triggering the corresponding HFCLK STOP task in between.

Application core frequency scaling

The application core clocks can be scaled from their respective HFCLK clocks.

The application core clock HCLK128M can at any time be scaled from the HFCLK128M clock using the HFCLKCTRL register.

The HCLK192M clock can be scaled from the HFCLK192M clock using the HFCLK192MCTRL register.

Note: Settings Div1 and Div2 in HFCLK192MCTRL register will result in increased power consumption.

The ACLK audio clock cannot be scaled from the HFCLKAUDIO clock. Instead, its frequency can be configured in the relevant peripherals. Refer to Audio oscillator for more information on audio clock and related peripherals.

Note: It is possible to scale the application core clocks at any time, for instance when a clock has already has been started, without having to stop it first.

32 MHz crystal oscillator (HFXO)

The 32 MHz crystal oscillator (HFXO) is controlled by a 32 MHz external crystal, see OSCILLATORS — Oscillator control.

Audio oscillator

The audio oscillator generates clock frequencies suitable for audio applications.

The audio oscillator has the following features:

Adjustable frequency with 3.3 ppm resolution in two frequency bands - 11.176 MHz to 11.402 MHz, and 12.165 MHz to 12.411 MHz
Low jitter, suitable for audio applications
Always uses the HFXO

The HFCLKAUDIO clock generated by the audio oscillator is suitable for use as the source clock in the I²S and PDM audio peripherals. In order to use this clock, it must be selected in the corresponding configuration registers in these peripherals. It is required to trigger the HFCLKAUDIOSTART task before it is used. To stop the HFCLKAUDIO clock, the HFCLKAUDIOSTOP task must be triggered. After triggering this task, the oscillator will be kept running as long as a peripheral is using it.

In applications where the audio data is arriving asynchronously to on-chip clocks, the frequency can be adjusted to stay in sync with the sender. The frequency can be configured in register HFCLKAUDIO.FREQUENCY using one of the following equations.

Figure 2. Calculating audio frequency f_out from register value

Figure 3. Calculating register value from audio frequency f_out

The acceptable HFCLKAUDIO.FREQUENCY register value ranges for the two frequency bands are listed in the following table.

When switching between the two frequency ranges, the peripherals must be stopped.

Table 3. HFCLKAUDIO.FREQUENCY register ranges
Frequency band	Register value and frequency
Frequency band	Min	Center	Max
11.176 MHz to 11.402 MHz	12519 (11.176 MHz)	15298 (11.289 MHz)	18068 (11.402 MHz)
12.165 MHz to 12.411 MHz	36834 (12.165 MHz)	39854 (12.288 MHz)	42874 (12.411 MHz)

Overriding the automatic HFCLK control system

Overriding the automatic clock control system is possible to ensure a HFCLK clock is started and kept running, even if not requested.

This can be used to avoid associated HFCLK clock start-up times and have the highest clock accuracy after wake-up from sleep.

The register HFCLKALWAYSRUN can override the automatic clock control system for the HFCLK128M/HFCLK64M clocks. This override is initiated by performing the following steps:

Set HFCLKSRC.SRC to select the HFCLK source.
Set HFCLKALWAYSRUN.ALWAYSRUN.
Trigger the HFCLKSTART task.

The register HFCLK192MALWAYSRUN can override the automatic clock control system for the HFCLK192M clock. This override is initiated by performing the following steps:

Set HFCLK192MSRC.SRC to select the HFCLK source.
Set HFCLK192MALWAYSRUN.ALWAYSRUN.
Trigger the HFCLK192MSTART task.

Registers HFCLKSRC/HFCLK192MSRC and HFCLKALWAYSRUN/HFCLK192MALWAYSRUN can be written at any time, but are only activated by the START task.

The register HFCLKAUDIOALWAYSRUN can override the automatic clock control system for the HFCLKAUDIO clock. The override is initiated by performing the following steps:

Set HFCLKAUDIOALWAYSRUN.ALWAYSRUN.
Trigger the HFCLKAUDIOSTART task.

Note: In this case, the HFCLK source is always the HFXO.

LFCLK controller

Each core has a number of low frequency clock (LFCLK) control instances. Each instance distributes one or more clocks to the core.

The LFCLK control instance in each core distributes the 32.768 kHz PCLK32KI peripheral clock to its corresponding core. The LFCLK clock is sourced from the power and clock subsystem to each LFCLK control instance.

In order to generate the LFCLK clock, the LFCLK controller uses the following LFCLK sources:

32.768 kHz RC oscillator (LFRC)
32.768 kHz crystal oscillator (LFXO)
32.768 kHz synthesized from HFCLK (LFSYNT)

For an illustration of the clock sources, see Clock control.

The LFCLK controller and all LFCLK sources are switched off in System OFF mode.

When peripherals require the PCLK32KI clock, such as RTC — Real-time counter and WDT — Watchdog timer, the LFCLK control will automatically request the LFCLK clock to the power and clock subsystem. The default LFCLK source is the LFRC.

When LFCLK control requests are stopped, LFCLK will stop requesting clock from the power and clock subsystem. If there are no LFCLK control requests from other cores, the power and clock subsystem will automatically stop the LFCLK clock and the LFRC source.

The LFCLK source may also be started by triggering the LFCLKSTART task. The LFCLK source is configured by selecting the preferred LFCLK source in register LFCLKSRC. Once selected, the LFCLK source will be started by triggering the LFCLKSTART task.

The LFCLK source can be configured at any time (for instance, when the LFCLK has already been started). The content of the LFCLKSRC register only takes effect when the LFCLKSTART task is triggered.

Note: Automatic requests of the LFCLK clock will ignore the value in LFCLKSRC and use LFRC as source, unless the LFCLK source is started by triggering the LFCLKSTART start. In this case, the LFCLK source will correspond to the value in LFCLKSRC when the LFCLKSTART start was last triggered.

The LFCLKSTARTED event will be generated after the LFCLKSTART task has been triggered and the LFCLK source has started. Triggering a LFCLKSTART task before the LFCLKSTARTED event from a previous LFCLKSTART task is generated will only generate one LFCLKSTARTED event. Triggering a LFCLKSTART task after a LFCLKSTARTED event is generated will generate a new LFCLKSTARTED event.

The LFCLK clock is stopped when nothing requests it, e.g. RTC — Real-time counter and WDT — Watchdog timer are stopped, and the LFCLKSTOP task is triggered. This must be done for all cores. Triggering the LFCLKSTOP task is required only if the LFCLKSTART task has been triggered before.

When the LFCLKSTART task is triggered, it is possible to trigger a new LFCLKSTART task without triggering a LFCLKSTOP task in between.

If the LFXO is selected as the LFCLK source, the LFCLK clock will initially start running from the LFRC while the LFXO is starting up, and then automatically switch to using the LFXO once this oscillator is running.

Events will be generated in the correct order, even if an LFCLK source that is already started by another LFCLK control instance is requested. The timing of events may differ, depending on whether a LFCLK source is already running or in the process of starting.

If two instances of the LFCLK control system request different LFCLK sources, the power and clock subsystem will secure that the most accurate of the requested LFCLK sources is selected. If one LFCLK control instance requests a particular LFCLK source to stop when another LFCLK control instance (or a peripheral) requests the same source to run, but at a lower accuracy, the power and clock subsystem will switch to the less accurate source. The following table summarizes the priorities of the LFCLK sources.

Table 4. LFCLK request priority
Priority	LFCLK source
Highest	LFSYNT
Second highest	LFXO
Lowest	LFRC

When switching the LFCLK source, such as from LFRC to LFXO, up to one LFCLK cycle may be lost.

32.768 kHz RC oscillator (LFRC)

An internal 32.768 kHz RC oscillator (LFRC) is available as the LFCLK source.

The LFRC oscillator is fully embedded in nRF5340 and does not require additional external components.

Calibrating the 32.768 kHz RC oscillator

To improve accuracy of the LFRC oscillator, it can be calibrated using the HFXO as a reference oscillator.

The LFRC oscillator can be calibrated while it is running. The calibration is started by triggering the CAL task which temporarily requests the HFCLK with the HFXO as the source for calibration.

A DONE event will be generated when the calibration is finished.

Note: Any core changing the LFCLK source will abort calibration without the DONE event being generated in the core triggering the CAL task.

If the CAL task is triggered while a calibration routine is already running (i.e. before the DONE event is generated), the CAL task has no effect and the calibration continues.

All cores can trigger the CAL task independently of each other. As a result, each core will receive a corresponding DONE event. If the calibration routine is already running (i.e. a core has triggered the CAL task), and the CAL task is triggered from another core, a DONE event is generated in both cores when the calibration of its corresponding LFRC oscillator is complete.

32.768 kHz crystal oscillator (LFXO)

For higher LFCLK accuracy (when greater than ± 250 ppm accuracy is required), the low frequency crystal oscillator (LFXO) must be used.

This clock source requires external components and GPIO pin configuration, see OSCILLATORS — Oscillator control.

32.768 kHz synthesized from HFCLK (LFSYNT)

The LFCLK can be synthesized from the HFCLK clock source.

LFSYNTH depends on the HFCLK to run. The accuracy of the LFCLK clock with the LFSYNTH as a source assumes the accuracy of the HFCLK. If high accuracy is required, the HFCLK must be generated from the HFXO.

Using the LFSYNT clock removes the requirement for an external 32.768 kHz crystal, but increases average power consumption as the HFCLK will need to be requested in the system.

Overriding the automatic LFCLK control system

Overriding the automatic clock control system to ensure the LFCLK clock is started and kept running is possible, even if not requested.

This can be used to avoid associated LFCLK clock start-up times and have the highest clock accuracy after wake-up from sleep.

The register LFCLKALWAYSRUN can override the automatic clock control system. This override is initiated by performing the following steps:

Set LFCLKSRC.SRC to select the LFCLK source.
Set LFCLKALWAYSRUN.ALWAYSRUN.
Trigger the LFCLKSTART task.

Registers LFCLKSRC.SRC and LFCLKALWAYSRUN.ALWAYSRUN can be written at any time, but are only activated by the LFCLKSTART task.

Registers

Table 5. Instances
Base address	Domain	Peripheral	Instance	Secure mapping	DMA security	Description	Configuration
0x50005000 0x40005000	APPLICATION	CLOCK	CLOCK : S CLOCK : NS	US	NA	Clock control
0x41005000	NETWORK	CLOCK	CLOCK	NS	NA	Clock control	HFCLKAUDIO not supported HFCLK192M not supported HFCLKCTRL reset value is 0x0.

Table 6. Register overview
Register	Offset	Description
TASKS_HFCLKSTART	0x000	Start HFCLK128M/HFCLK64M source as selected in HFCLKSRC
TASKS_HFCLKSTOP	0x004	Stop HFCLK128M/HFCLK64M source
TASKS_LFCLKSTART	0x008	Start LFCLK source as selected in LFCLKSRC
TASKS_LFCLKSTOP	0x00C	Stop LFCLK source
TASKS_CAL	0x010	Start calibration of LFRC oscillator
TASKS_HFCLKAUDIOSTART	0x018	Start HFCLKAUDIO source
TASKS_HFCLKAUDIOSTOP	0x01C	Stop HFCLKAUDIO source
TASKS_HFCLK192MSTART	0x020	Start HFCLK192M source as selected in HFCLK192MSRC
TASKS_HFCLK192MSTOP	0x024	Stop HFCLK192M source
SUBSCRIBE_HFCLKSTART	0x080	Subscribe configuration for task HFCLKSTART
SUBSCRIBE_HFCLKSTOP	0x084	Subscribe configuration for task HFCLKSTOP
SUBSCRIBE_LFCLKSTART	0x088	Subscribe configuration for task LFCLKSTART
SUBSCRIBE_LFCLKSTOP	0x08C	Subscribe configuration for task LFCLKSTOP
SUBSCRIBE_CAL	0x090	Subscribe configuration for task CAL
SUBSCRIBE_HFCLKAUDIOSTART	0x098	Subscribe configuration for task HFCLKAUDIOSTART
SUBSCRIBE_HFCLKAUDIOSTOP	0x09C	Subscribe configuration for task HFCLKAUDIOSTOP
SUBSCRIBE_HFCLK192MSTART	0x0A0	Subscribe configuration for task HFCLK192MSTART
SUBSCRIBE_HFCLK192MSTOP	0x0A4	Subscribe configuration for task HFCLK192MSTOP
EVENTS_HFCLKSTARTED	0x100	HFCLK128M/HFCLK64M source started
EVENTS_LFCLKSTARTED	0x104	LFCLK source started
EVENTS_DONE	0x11C	Calibration of LFRC oscillator complete event
EVENTS_HFCLKAUDIOSTARTED	0x120	HFCLKAUDIO source started
EVENTS_HFCLK192MSTARTED	0x124	HFCLK192M source started
PUBLISH_HFCLKSTARTED	0x180	Publish configuration for event HFCLKSTARTED
PUBLISH_LFCLKSTARTED	0x184	Publish configuration for event LFCLKSTARTED
PUBLISH_DONE	0x19C	Publish configuration for event DONE
PUBLISH_HFCLKAUDIOSTARTED	0x1A0	Publish configuration for event HFCLKAUDIOSTARTED
PUBLISH_HFCLK192MSTARTED	0x1A4	Publish configuration for event HFCLK192MSTARTED
INTEN	0x300	Enable or disable interrupt
INTENSET	0x304	Enable interrupt
INTENCLR	0x308	Disable interrupt
INTPEND	0x30C	Pending interrupts
HFCLKRUN	0x408	Status indicating that HFCLKSTART task has been triggered
HFCLKSTAT	0x40C	Status indicating which HFCLK128M/HFCLK64M source is running This register value in any CLOCK instance reflects status only due to configurations/actions in that CLOCK instance.
LFCLKRUN	0x414	Status indicating that LFCLKSTART task has been triggered
LFCLKSTAT	0x418	Status indicating which LFCLK source is running This register value in any CLOCK instance reflects status only due to configurations/actions in that CLOCK instance.
LFCLKSRCCOPY	0x41C	Copy of LFCLKSRC register, set when LFCLKSTART task was triggered
HFCLKAUDIORUN	0x450	Status indicating that HFCLKAUDIOSTART task has been triggered
HFCLKAUDIOSTAT	0x454	Status indicating which HFCLKAUDIO source is running
HFCLK192MRUN	0x458	Status indicating that HFCLK192MSTART task has been triggered
HFCLK192MSTAT	0x45C	Status indicating which HFCLK192M source is running
HFCLKSRC	0x514	Clock source for HFCLK128M/HFCLK64M
LFCLKSRC	0x518	Clock source for LFCLK
HFCLKCTRL	0x558	HFCLK128M frequency configuration
HFCLKAUDIO.FREQUENCY	0x55C	Audio PLL frequency in 11.176 MHz - 11.402 MHz or 12.165 MHz - 12.411 MHz frequency bands
HFCLKALWAYSRUN	0x570	Automatic or manual control of HFCLK128M/HFCLK64M
LFCLKALWAYSRUN	0x574	Automatic or manual control of LFCLK
HFCLKAUDIOALWAYSRUN	0x57C	Automatic or manual control of HFCLKAUDIO
HFCLK192MSRC	0x580	Clock source for HFCLK192M
HFCLK192MALWAYSRUN	0x584	Automatic or manual control of HFCLK192M
HFCLK192MCTRL	0x5B8	HFCLK192M frequency configuration

TASKS_HFCLKSTART

Address offset: 0x000

Start HFCLK128M/HFCLK64M source as selected in HFCLKSRC

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	TASKS_HFCLKSTART										Start HFCLK128M/HFCLK64M source as selected in HFCLKSRC
			Trigger	1								Trigger task

TASKS_HFCLKSTOP

Address offset: 0x004

Stop HFCLK128M/HFCLK64M source

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	TASKS_HFCLKSTOP										Stop HFCLK128M/HFCLK64M source
			Trigger	1								Trigger task

TASKS_LFCLKSTART

Address offset: 0x008

Start LFCLK source as selected in LFCLKSRC

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	TASKS_LFCLKSTART										Start LFCLK source as selected in LFCLKSRC
			Trigger	1								Trigger task

TASKS_LFCLKSTOP

Address offset: 0x00C

Stop LFCLK source

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	TASKS_LFCLKSTOP										Stop LFCLK source
			Trigger	1								Trigger task

TASKS_CAL

Address offset: 0x010

Start calibration of LFRC oscillator

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	TASKS_CAL										Start calibration of LFRC oscillator
			Trigger	1								Trigger task

TASKS_HFCLKAUDIOSTART

Address offset: 0x018

Start HFCLKAUDIO source

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	TASKS_HFCLKAUDIOSTART										Start HFCLKAUDIO source
			Trigger	1								Trigger task

TASKS_HFCLKAUDIOSTOP

Address offset: 0x01C

Stop HFCLKAUDIO source

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	TASKS_HFCLKAUDIOSTOP										Stop HFCLKAUDIO source
			Trigger	1								Trigger task

TASKS_HFCLK192MSTART

Address offset: 0x020

Start HFCLK192M source as selected in HFCLK192MSRC

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	TASKS_HFCLK192MSTART										Start HFCLK192M source as selected in HFCLK192MSRC
			Trigger	1								Trigger task

TASKS_HFCLK192MSTOP

Address offset: 0x024

Stop HFCLK192M source

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	TASKS_HFCLK192MSTOP										Stop HFCLK192M source
			Trigger	1								Trigger task

SUBSCRIBE_HFCLKSTART

Address offset: 0x080

Subscribe configuration for task HFCLKSTART

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B																								A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CHIDX		[255..0]								DPPI channel that task HFCLKSTART will subscribe to
B	RW	EN
			Disabled	0								Disable subscription
			Enabled	1								Enable subscription

SUBSCRIBE_HFCLKSTOP

Address offset: 0x084

Subscribe configuration for task HFCLKSTOP

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B																								A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CHIDX		[255..0]								DPPI channel that task HFCLKSTOP will subscribe to
B	RW	EN
			Disabled	0								Disable subscription
			Enabled	1								Enable subscription

SUBSCRIBE_LFCLKSTART

Address offset: 0x088

Subscribe configuration for task LFCLKSTART

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B																								A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CHIDX		[255..0]								DPPI channel that task LFCLKSTART will subscribe to
B	RW	EN
			Disabled	0								Disable subscription
			Enabled	1								Enable subscription

SUBSCRIBE_LFCLKSTOP

Address offset: 0x08C

Subscribe configuration for task LFCLKSTOP

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B																								A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CHIDX		[255..0]								DPPI channel that task LFCLKSTOP will subscribe to
B	RW	EN
			Disabled	0								Disable subscription
			Enabled	1								Enable subscription

SUBSCRIBE_CAL

Address offset: 0x090

Subscribe configuration for task CAL

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B																								A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CHIDX		[255..0]								DPPI channel that task CAL will subscribe to
B	RW	EN
			Disabled	0								Disable subscription
			Enabled	1								Enable subscription

SUBSCRIBE_HFCLKAUDIOSTART

Address offset: 0x098

Subscribe configuration for task HFCLKAUDIOSTART

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B																								A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CHIDX		[255..0]								DPPI channel that task HFCLKAUDIOSTART will subscribe to
B	RW	EN
			Disabled	0								Disable subscription
			Enabled	1								Enable subscription

SUBSCRIBE_HFCLKAUDIOSTOP

Address offset: 0x09C

Subscribe configuration for task HFCLKAUDIOSTOP

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B																								A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CHIDX		[255..0]								DPPI channel that task HFCLKAUDIOSTOP will subscribe to
B	RW	EN
			Disabled	0								Disable subscription
			Enabled	1								Enable subscription

SUBSCRIBE_HFCLK192MSTART

Address offset: 0x0A0

Subscribe configuration for task HFCLK192MSTART

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B																								A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CHIDX		[255..0]								DPPI channel that task HFCLK192MSTART will subscribe to
B	RW	EN
			Disabled	0								Disable subscription
			Enabled	1								Enable subscription

SUBSCRIBE_HFCLK192MSTOP

Address offset: 0x0A4

Subscribe configuration for task HFCLK192MSTOP

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B																								A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CHIDX		[255..0]								DPPI channel that task HFCLK192MSTOP will subscribe to
B	RW	EN
			Disabled	0								Disable subscription
			Enabled	1								Enable subscription

EVENTS_HFCLKSTARTED

Address offset: 0x100

HFCLK128M/HFCLK64M source started

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EVENTS_HFCLKSTARTED										HFCLK128M/HFCLK64M source started
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_LFCLKSTARTED

Address offset: 0x104

LFCLK source started

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EVENTS_LFCLKSTARTED										LFCLK source started
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_DONE

Address offset: 0x11C

Calibration of LFRC oscillator complete event

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EVENTS_DONE										Calibration of LFRC oscillator complete event
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_HFCLKAUDIOSTARTED

Address offset: 0x120

HFCLKAUDIO source started

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EVENTS_HFCLKAUDIOSTARTED										HFCLKAUDIO source started
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_HFCLK192MSTARTED

Address offset: 0x124

HFCLK192M source started

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EVENTS_HFCLK192MSTARTED										HFCLK192M source started
			NotGenerated	0								Event not generated
			Generated	1								Event generated

PUBLISH_HFCLKSTARTED

Address offset: 0x180

Publish configuration for event HFCLKSTARTED

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B																								A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CHIDX		[255..0]								DPPI channel that event HFCLKSTARTED will publish to.
B	RW	EN
			Disabled	0								Disable publishing
			Enabled	1								Enable publishing

PUBLISH_LFCLKSTARTED

Address offset: 0x184

Publish configuration for event LFCLKSTARTED

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B																								A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CHIDX		[255..0]								DPPI channel that event LFCLKSTARTED will publish to.
B	RW	EN
			Disabled	0								Disable publishing
			Enabled	1								Enable publishing

PUBLISH_DONE

Address offset: 0x19C

Publish configuration for event DONE

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B																								A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CHIDX		[255..0]								DPPI channel that event DONE will publish to.
B	RW	EN
			Disabled	0								Disable publishing
			Enabled	1								Enable publishing

PUBLISH_HFCLKAUDIOSTARTED

Address offset: 0x1A0

Publish configuration for event HFCLKAUDIOSTARTED

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B																								A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CHIDX		[255..0]								DPPI channel that event HFCLKAUDIOSTARTED will publish to.
B	RW	EN
			Disabled	0								Disable publishing
			Enabled	1								Enable publishing

PUBLISH_HFCLK192MSTARTED

Address offset: 0x1A4

Publish configuration for event HFCLK192MSTARTED

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B																								A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CHIDX		[255..0]								DPPI channel that event HFCLK192MSTARTED will publish to.
B	RW	EN
			Disabled	0								Disable publishing
			Enabled	1								Enable publishing

INTEN

Address offset: 0x300

Enable or disable interrupt

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																										E	D	C						B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	HFCLKSTARTED										Enable or disable interrupt for event HFCLKSTARTED
			Disabled	0								Disable
			Enabled	1								Enable
B	RW	LFCLKSTARTED										Enable or disable interrupt for event LFCLKSTARTED
			Disabled	0								Disable
			Enabled	1								Enable
C	RW	DONE										Enable or disable interrupt for event DONE
			Disabled	0								Disable
			Enabled	1								Enable
D	RW	HFCLKAUDIOSTARTED										Enable or disable interrupt for event HFCLKAUDIOSTARTED
			Disabled	0								Disable
			Enabled	1								Enable
E	RW	HFCLK192MSTARTED										Enable or disable interrupt for event HFCLK192MSTARTED
			Disabled	0								Disable
			Enabled	1								Enable

INTENSET

Address offset: 0x304

Enable interrupt

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																										E	D	C						B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	HFCLKSTARTED										Write '1' to enable interrupt for event HFCLKSTARTED
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
B	RW	LFCLKSTARTED										Write '1' to enable interrupt for event LFCLKSTARTED
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
C	RW	DONE										Write '1' to enable interrupt for event DONE
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
D	RW	HFCLKAUDIOSTARTED										Write '1' to enable interrupt for event HFCLKAUDIOSTARTED
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
E	RW	HFCLK192MSTARTED										Write '1' to enable interrupt for event HFCLK192MSTARTED
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled

INTENCLR

Address offset: 0x308

Disable interrupt

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																										E	D	C						B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	HFCLKSTARTED										Write '1' to disable interrupt for event HFCLKSTARTED
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
B	RW	LFCLKSTARTED										Write '1' to disable interrupt for event LFCLKSTARTED
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
C	RW	DONE										Write '1' to disable interrupt for event DONE
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
D	RW	HFCLKAUDIOSTARTED										Write '1' to disable interrupt for event HFCLKAUDIOSTARTED
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
E	RW	HFCLK192MSTARTED										Write '1' to disable interrupt for event HFCLK192MSTARTED
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled

INTPEND

Address offset: 0x30C

Pending interrupts

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																										E	D	C						B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	HFCLKSTARTED										Read pending status of interrupt for event HFCLKSTARTED
			NotPending	0								Read: Not pending
			Pending	1								Read: Pending
B	R	LFCLKSTARTED										Read pending status of interrupt for event LFCLKSTARTED
			NotPending	0								Read: Not pending
			Pending	1								Read: Pending
C	R	DONE										Read pending status of interrupt for event DONE
			NotPending	0								Read: Not pending
			Pending	1								Read: Pending
D	R	HFCLKAUDIOSTARTED										Read pending status of interrupt for event HFCLKAUDIOSTARTED
			NotPending	0								Read: Not pending
			Pending	1								Read: Pending
E	R	HFCLK192MSTARTED										Read pending status of interrupt for event HFCLK192MSTARTED
			NotPending	0								Read: Not pending
			Pending	1								Read: Pending

HFCLKRUN

Address offset: 0x408

Status indicating that HFCLKSTART task has been triggered

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	STATUS										HFCLKSTART task triggered or not
			NotTriggered	0								Task not triggered
			Triggered	1								Task triggered

HFCLKSTAT

Address offset: 0x40C

Status indicating which HFCLK128M/HFCLK64M source is running

This register value in any CLOCK instance reflects status only due to configurations/actions in that CLOCK instance.

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																			C												B				A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	SRC										Active clock source
			HFINT	0								Clock source: HFINT - 128 MHz on-chip oscillator
			HFXO	1								Clock source: HFXO - 128 MHz clock derived from external 32 MHz crystal oscillator
B	R	ALWAYSRUNNING										ALWAYSRUN activated
			NotRunning	0								Automatic clock control enabled
			Running	1								Oscillator is always running
C	R	STATE										HFCLK state
			NotRunning	0								HFCLK not running
			Running	1