UICR — User information configuration registers

The user information configuration registers (UICRs) are non-volatile memory (NVM) registers for configuring user-specific settings.

For information on writing UICR registers, see the NVMC — Non-volatile memory controller and Memory chapters.

Registers

Table 1. Instances
Base address Peripheral Instance Description Configuration
0x10001000 UICR UICR

User information configuration

    
Table 2. Register overview
Register Offset Description
UNUSED0 0x000  

Reserved
UNUSED1 0x004  

Reserved
UNUSED2 0x008  

Reserved
UNUSED3 0x010  

Reserved
NRFFW[0] 0x014

Reserved for Nordic firmware design

  
NRFFW[1] 0x018

Reserved for Nordic firmware design

  
NRFFW[2] 0x01C

Reserved for Nordic firmware design

  
NRFFW[3] 0x020

Reserved for Nordic firmware design

  
NRFFW[4] 0x024

Reserved for Nordic firmware design

  
NRFFW[5] 0x028

Reserved for Nordic firmware design

  
NRFFW[6] 0x02C

Reserved for Nordic firmware design

  
NRFFW[7] 0x030

Reserved for Nordic firmware design

  
NRFFW[8] 0x034

Reserved for Nordic firmware design

  
NRFFW[9] 0x038

Reserved for Nordic firmware design

  
NRFFW[10] 0x03C

Reserved for Nordic firmware design

  
NRFFW[11] 0x040

Reserved for Nordic firmware design

  
NRFFW[12] 0x044

Reserved for Nordic firmware design

  
NRFHW[0] 0x050

Reserved for Nordic hardware design

  
NRFHW[1] 0x054

Reserved for Nordic hardware design

  
NRFHW[2] 0x058

Reserved for Nordic hardware design

  
NRFHW[3] 0x05C

Reserved for Nordic hardware design

  
NRFHW[4] 0x060

Reserved for Nordic hardware design

  
NRFHW[5] 0x064

Reserved for Nordic hardware design

  
NRFHW[6] 0x068

Reserved for Nordic hardware design

  
NRFHW[7] 0x06C

Reserved for Nordic hardware design

  
NRFHW[8] 0x070

Reserved for Nordic hardware design

  
NRFHW[9] 0x074

Reserved for Nordic hardware design

  
NRFHW[10] 0x078

Reserved for Nordic hardware design

  
NRFHW[11] 0x07C

Reserved for Nordic hardware design

  
CUSTOMER[0] 0x080

Reserved for customer

  
CUSTOMER[1] 0x084

Reserved for customer

  
CUSTOMER[2] 0x088

Reserved for customer

  
CUSTOMER[3] 0x08C

Reserved for customer

  
CUSTOMER[4] 0x090

Reserved for customer

  
CUSTOMER[5] 0x094

Reserved for customer

  
CUSTOMER[6] 0x098

Reserved for customer

  
CUSTOMER[7] 0x09C

Reserved for customer

  
CUSTOMER[8] 0x0A0

Reserved for customer

  
CUSTOMER[9] 0x0A4

Reserved for customer

  
CUSTOMER[10] 0x0A8

Reserved for customer

  
CUSTOMER[11] 0x0AC

Reserved for customer

  
CUSTOMER[12] 0x0B0

Reserved for customer

  
CUSTOMER[13] 0x0B4

Reserved for customer

  
CUSTOMER[14] 0x0B8

Reserved for customer

  
CUSTOMER[15] 0x0BC

Reserved for customer

  
CUSTOMER[16] 0x0C0

Reserved for customer

  
CUSTOMER[17] 0x0C4

Reserved for customer

  
CUSTOMER[18] 0x0C8

Reserved for customer

  
CUSTOMER[19] 0x0CC

Reserved for customer

  
CUSTOMER[20] 0x0D0

Reserved for customer

  
CUSTOMER[21] 0x0D4

Reserved for customer

  
CUSTOMER[22] 0x0D8

Reserved for customer

  
CUSTOMER[23] 0x0DC

Reserved for customer

  
CUSTOMER[24] 0x0E0

Reserved for customer

  
CUSTOMER[25] 0x0E4

Reserved for customer

  
CUSTOMER[26] 0x0E8

Reserved for customer

  
CUSTOMER[27] 0x0EC

Reserved for customer

  
CUSTOMER[28] 0x0F0

Reserved for customer

  
CUSTOMER[29] 0x0F4

Reserved for customer

  
CUSTOMER[30] 0x0F8

Reserved for customer

  
CUSTOMER[31] 0x0FC

Reserved for customer

  
PSELRESET[0] 0x200

Mapping of the nRESET function (see POWER chapter for details)

  
PSELRESET[1] 0x204

Mapping of the nRESET function (see POWER chapter for details)

  
APPROTECT 0x208

Access port protection

  
NFCPINS 0x20C

Setting of pins dedicated to NFC functionality: NFC antenna or GPIO

  
DEBUGCTRL 0x210

Processor debug control

  
REGOUT0 0x304

Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - V_VDDH-VDD.

  

NRFFW[n] (n=0..12)

Address offset: 0x014 + (n × 0x4)

Reserved for Nordic firmware design

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID Access Field Value ID Value Description
A RW

NRFFW

    

Reserved for Nordic firmware design

NRFHW[n] (n=0..11)

Address offset: 0x050 + (n × 0x4)

Reserved for Nordic hardware design

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID Access Field Value ID Value Description
A RW

NRFHW

    

Reserved for Nordic hardware design

CUSTOMER[n] (n=0..31)

Address offset: 0x080 + (n × 0x4)

Reserved for customer

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID Access Field Value ID Value Description
A RW

CUSTOMER

    

Reserved for customer

PSELRESET[n] (n=0..1)

Address offset: 0x200 + (n × 0x4)

Mapping of the nRESET function (see POWER chapter for details)

All PSELRESET registers have to contain the same value for a pin mapping to be valid. If values are not the same, there will be no nRESET function exposed on a GPIO. As a result, the device will always start independently of the levels present on any of the GPIOs.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID C                                                  

B

 A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID Access Field Value ID Value Description
A RW

PIN

  

18

GPIO pin number onto which nRESET is exposed

B RW

PORT

  

0

Port number onto which nRESET is exposed

C RW

CONNECT

    

Connection

     

Disconnected

1

Disconnect

     

Connected

0

Connect

APPROTECT

Address offset: 0x208

Access port protection

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                 A A A A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID Access Field Value ID Value Description
A RW

PALL

    

Enable or disable access port protection.

See Debug and trace for more information.

     

Disabled

0xFF

Hardware disable of access port protection for devices where access port protection is controlled by hardware

     

HwDisabled

0x5A

Hardware disable of access port protection for devices where access port protection is controlled by hardware and software

     

Enabled

0x00

Enable

NFCPINS

Address offset: 0x20C

Setting of pins dedicated to NFC functionality: NFC antenna or GPIO

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                              

A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID Access Field Value ID Value Description
A RW

PROTECT

    

Setting of pins dedicated to NFC functionality

     

Disabled

0

Operation as GPIO pins. Same protection as normal GPIO pins.

     

NFC

1

Operation as NFC antenna pins. Configures the protection for NFC operation.

DEBUGCTRL

Address offset: 0x210

Processor debug control

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                

B

B

B

B

B

B

B

B

A

A

A

A

A

A

A

A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID Access Field Value ID Value Description
A RW

CPUNIDEN

    

Configure CPU non-intrusive debug features

     

Enabled

0xFF

Enable CPU ITM and ETM functionality (default behavior)

     

Disabled

0x00

Disable CPU ITM and ETM functionality

B RW

CPUFPBEN

    

Configure CPU flash patch and breakpoint (FPB) unit behavior

     

Enabled

0xFF

Enable CPU FPB unit (default behavior)

     

Disabled

0x00

Disable CPU FPB unit. Writes into the FPB registers will be ignored.

REGOUT0

Address offset: 0x304

Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - V_VDDH-VDD.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                          

A

A

A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID Access Field Value ID Value Description
A RW

VOUT

    

Output voltage from REG0 regulator stage.

     

1V8

0

1.8 V

     

2V1

1

2.1 V

     

2V4

2

2.4 V

     

2V7

3

2.7 V

     

3V0

4

3.0 V

     

3V3

5

3.3 V

     

DEFAULT

7

Default voltage: 1.8 V